In article <m2n.1IE31l-00ETia@chiark.greenend.org.uk> you write:
>Does anybody have an idea of how HyperSPARC support is doing, both SMP
>and UP (e.g., with ROSS RT625/RT626 modules)?

Well, I've been running a SS20 with two HyperSPARCs for a year or two 
now:

NetBSD 2.1 (HMM) #0: Mon Oct 31 22:36:15 GMT 2005
        bjh21@viking:/var/tmp/NetBSD-2.1/usr/src/sys/arch/sparc/compile/obj/HMM
total memory = 159 MB
avail memory = 151 MB
bootpath: /iommu@f,e0000000/sbus@f,e0001000/espdma@f,400000/esp@f,800000/sd@3,0
mainbus0 (root): SUNW,SPARCstation-20: hostid 727a5ea6
cpu0 at mainbus0: mid 8: RT620/625 @ 150 MHz, on-chip FPU
cpu0: 512K byte write-back, 32 bytes/line, sw flush: cache enabled
cpu1 at mainbus0: mid 10: RT620/625 @ 150 MHz, on-chip FPU
cpu1: 512K byte write-back, 32 bytes/line, sw flush: cache enabled

As far as I can tell, it works.

-- 
Ben Harris