On Mon, Jul 09, 2007 at 11:33:21AM +0200, Havard Eidnes wrote:
> mainbus0 (root): SUNW,SPARCstation-10: hostid 72602c4a
> cpu0 at mainbus0: mid 8: TMS390Z50 v0 or TMS390Z55 @ 50 MHz, on-chip FPU
> cpu0: physical 20K instruction (64 b/l), 16K data (32 b/l), 1024K external (32 b/l): cache enabled
> cpu1 at mainbus0: mid 10: TMS390Z50 v0 or TMS390Z55 @ 50 MHz, on-chip FPU
> cpu1: physical 20K instruction (64 b/l), 16K data (32 b/l), 1024K external (32 b/l): cache enabled

Those are slightly different from Aaron's - he has SM50s, without L2 cache.
I had problems with SM50s in an SMP config with 3.0, although they worked
fine with 2.1. 

-mj
-- 
Michael-John Turner | http://mjturner.net/
mj@turner.org.za    | Open Source in WC ZA - http://www.clug.org.za/