Subject: Re: building -current, CPU optimizations, and the 'sh' problem.
To: John D. Baker <jdbaker@mylinuxisp.com>
From: Rui Paulo <rpaulo@fnop.net>
List: port-sparc
Date: 10/15/2005 01:36:49
--IA03tywDYuoVKXrw
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
Content-Transfer-Encoding: quoted-printable

On 2005.10.14 19:08:03 -0500, John D. Baker wrote:
| On Fri, 14 Oct 2005, Rui Paulo wrote:
|=20
| > Do you know the ammount of CPU cache both systems have?
|=20
| The SS5-110 has:
|=20
| mainbus0 (root): SUNW,SPARCstation-5: hostid 807a1b43
| cpu0 at mainbus0: MB86904 @ 110 MHz, on-chip FPU
| cpu0: 16K instruction (32 b/l), 8K data (16 b/l): cache enabled
|=20
|=20
| The SS20-2xHS150 has:
|=20
| mainbus0 (root): SUNW,SPARCstation-20: hostid 72818dfe
| cpu0 at mainbus0: mid 8: RT620/625 @ 150 MHz, on-chip FPU
| cpu0: 512K byte write-back, 32 bytes/line, sw flush: cache enabled
| cpu1 at mainbus0: mid 10: RT620/625 @ 150 MHz, on-chip FPU
| cpu1: 512K byte write-back, 32 bytes/line, sw flush: cache enabled

Also, do you know if your CPUs have external cache? I think that
information is only available from the PROM.

		-- Rui Paulo

--IA03tywDYuoVKXrw
Content-Type: application/pgp-signature
Content-Disposition: inline

-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.2 (NetBSD)

iD4DBQFDUE8hZPqyxs9FH4QRAiLNAJdfLkCOlrsIo6jwAK69SOWI+2ekAKCcTBpG
DTVxuSQWHM/sD3SNt5ma7A==
=Ljxo
-----END PGP SIGNATURE-----

--IA03tywDYuoVKXrw--