Subject: Re: "Bad pAUX_base" again
To: Rui Paulo <firstname.lastname@example.org>
From: khaqq <email@example.com>
Date: 10/07/2005 14:35:21
On Fri, 7 Oct 2005 13:22:27 +0100
Rui Paulo <firstname.lastname@example.org> wrote:
> On 2005.10.07 14:21:46 +0200, khaqq wrote:
> | I seem to remember using cacheless CPUs in SMP mode isn't a recommended
> | configuration.
> Why is that so ? I think all the CPUs we are talking about have some
> form of minimal cache.
from http://mbus.sunhelp.org/modules/index.htm#2.1 :
"Maximum of 1 such module per MBus: these modules did not properly
adhere to the MBus Level 2 (multiprocessor) protocol."
This was about SM40s though, according to the site SM50s may be fine.
from http://faqaboss.sunhelp.org/new/arch.html :
"The following combinations probably work but are unsupported:
* 2 x SM50 (...)"