Subject: Re: "Bad pAUX_base" again
To: Bruce O'Neel <email@example.com>
From: khaqq <firstname.lastname@example.org>
Date: 10/07/2005 14:21:46
On Fri, 7 Oct 2005 10:06:54 +0000
"Bruce O'Neel" <email@example.com> wrote:
> Sorry this isn't a true followup. Back around 5/9 through 9/9 there
> was chatter about Bad pAUX_base and which systems this occured on. I
> finally got the time and put a 60mhz SuperSparc in a SS20 and did a
> build.sh run. 3 days later and we don't have any cores nor Bad
> pAUX_base messages in the build log.
> So, the current status seems to be:
> - MicroSparc IIs @ 110mhz in SS4 and SS5 system. Yes, you get it.
> (me SS4, Laurent FAILLIE SS5)
> - SparcBook and Krups with basically the same CPUs, yes. (Michael)
> - Dual Supersparc @ 50mhz in a SS20. Yes, so often that it is
> unusable. (Rui Paulo)
> - Tri hypersparc @ different mhz in a SS20. I've never seen it. I've
> also not seen it with assorted other hypersparc combos that I've run
> over time. They all have been rock solid. (me)
> - Single supersparc @ 60mhz in a SS20, seems not. (me)
> - one has to assume that some other types of systems are ok otherwise
> there would be more chatter about this.
> Is it the level 2 cache? (I'm frowning but you can't see that) The
> microsparc IIs don't have it. My hypersparcs do, and so does my
> Rui Paulo, according the the snippet of your dmesg, your 50mhz CPUs
> don't. What exact part numbers are they?
I seem to remember using cacheless CPUs in SMP mode isn't a recommended
configuration. This may not matter with the current problem (or could be
a Solaris limitation) since the single CPU SS5 seem to get this bug too.
I can test with a SS10 + 2x SM71, a TurboSparc SS5, a MicroSparc-II SS5,
and a MicroSparc LX. Will testing this snapshot be of any help ? :