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On Mon, May 09, 2005 at 11:46:01AM +0200, Bernd Sieker wrote:
> On 08.05.05, 22:06:27, Malte Dehling wrote:
> >=20
> > I've been running NetBSD 1.6 and 2.0 on my SparcStation 20 with a 50MHz
> > SuperSparc without cache (501-2708-072152) for a long time and I never =
had any
> > problems. Last week I got 2 75MHz SuperSparc II CPUs with 1MB cache each
> > (501-2520) and as my prom rev is 2.22 (minimum required according to
> > http://mbus.sunhelp.org/systems/sun/ss20.htm) I expected them to work w=
ithout
> > problems, which was not the case...
> >=20
> > According to the person I got these from, the modules are tested and sh=
ould be
> > ok. I took care when putting them in their place so I think its not som=
ething I
> > did, physically...
> >=20
> > Anyway, when I turned on the SS/20 I got a `Power On Self Test', then I=
 got a
> > `Data Access Exception'. After doing a reset at the ok prompt, the SS/2=
0 boots
>=20
> I really only got those with broken CPU modules, so my educated
> guess is that module #0 is slightly broken and #2 is totally gone.
> The module that I have that causes Data Access Exceptions works
> almost ok for some time in UP and MP (together with a flawless
> module) operation and then causes random problems later, applications
> segfaulting, kernel panics, etc.

I dont have another SS10/20 right now, to test if its really the modules, b=
ut
it looks indeed as if something were broken. I will do some stress-testing =
with
the `slightly broken' module tomorrow, just to see what happens.
Im still wondering why I get memory errors? Are they caused by a bad CPU?

>=20
> > Could it be something with the mainboard rev or so? IIRC some Ultra-2 s=
 for
> > example can only have UltraSparc I CPUs...
>=20
> SM71 should really work in all SS20 revisions, it even works in SS10.
>=20
> A later PROM would be nice in that it also shows the cache controller
> revision (which can be 3.x or 4.x for 75MHz Modules). The heatsinks
> on 3.x vs. 4.x modules look slightly different, but I forget which
> are which. (Either way, both should work fine, mixing them is not
> recommended, though.)
>=20
> --=20
> Bernd Sieker

The two modules are both 501-2520, and:
<#0> ok module-info
MBus  :  50 MHz=20
SBus  :  25 MHz=20
CPU#0 :  75 MHz SuperSPARC-II / SuperCache  3.1/3.3=20
CPU#2 :  75 MHz SuperSPARC-II / SuperCache  3.1/3.3=20
---
According to http://mbus.sunhelp.org/modules/index.htm, this module has
MXCC 3.3.=20

--=20
Malte Dehling

Mail:		mdehling [at] math.ruhr-uni-bochum.de
Website:	http://mdehling.ath.cx/
PGP:		2586 A3BF B438 E68E 2B85  C4EA C5A7 AD96 C865 03D2

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