On 08.05.05, 22:06:27, Malte Dehling wrote:
> 
> I've been running NetBSD 1.6 and 2.0 on my SparcStation 20 with a 50MHz
> SuperSparc without cache (501-2708-072152) for a long time and I never had any
> problems. Last week I got 2 75MHz SuperSparc II CPUs with 1MB cache each
> (501-2520) and as my prom rev is 2.22 (minimum required according to
> http://mbus.sunhelp.org/systems/sun/ss20.htm) I expected them to work without
> problems, which was not the case...
> 
> According to the person I got these from, the modules are tested and should be
> ok. I took care when putting them in their place so I think its not something I
> did, physically...
> 
> Anyway, when I turned on the SS/20 I got a `Power On Self Test', then I got a
> `Data Access Exception'. After doing a reset at the ok prompt, the SS/20 boots

I really only got those with broken CPU modules, so my educated
guess is that module #0 is slightly broken and #2 is totally gone.
The module that I have that causes Data Access Exceptions works
almost ok for some time in UP and MP (together with a flawless
module) operation and then causes random problems later, applications
segfaulting, kernel panics, etc.

> Could it be something with the mainboard rev or so? IIRC some Ultra-2 s for
> example can only have UltraSparc I CPUs...

SM71 should really work in all SS20 revisions, it even works in SS10.

A later PROM would be nice in that it also shows the cache controller
revision (which can be 3.x or 4.x for 75MHz Modules). The heatsinks
on 3.x vs. 4.x modules look slightly different, but I forget which
are which. (Either way, both should work fine, mixing them is not
recommended, though.)

> 
> ---
> Malte Dehling

-- 
Bernd Sieker

NetBSD: Networking Space
		-- Andrew Gillham