I've been playing with a quad processor SS20. Unfortunately it has  
mismatched cache size between the two processor modules. One has 256KB  
caches, the other 512KB.

While I'm aware that I'm pretty much on my own running such a  
configuration I noticed that it wasn't reporting the cache sizes of the  
processors correctly when I has the 256KB cache ones in first. What  
happened is the boot CPU was reported (incorrectly) as having 512KB  
cache.

Some some output from the box to see what I mean. In the second one  
I've swapped the modules and they're now reported correctly.

The two outputs are from different kernels, the second kernel showed  
the same problem but I was booting into single-user at the time so it  
didn't get logged. When I switched the modules over the result was  
correct output.

=============================
NetBSD 2.0_BETA (GENERIC.MP) #0: Wed Aug 18 16:09:44 UTC 2004
        
autobuild@tgm.netbsd.org:/autobuild/netbsd-2-0/sparc/OBJ/autobuild/ 
netbsd-2-0/src/sys/arch/sparc/compile/GENERIC.MP

mainbus0 (root): SUNW,SPARCstation-20: hostid 72832b61
cpu0 at mainbus0: mid 8: RT620/625 @ 125 MHz, on-chip FPU
cpu0: 512K byte write-back, 32 bytes/line, sw flush: cache enabled
cpu1 at mainbus0: mid 9: RT620/625 @ 125 MHz, on-chip FPU
cpu1: 256K byte write-back, 64 bytes/line, sw flush: cache enabled
cpu2 at mainbus0: mid 10: RT620/625 @ 125 MHz, on-chip FPU
cpu2: 512K byte write-back, 32 bytes/line, sw flush: cache enabled
cpu3 at mainbus0: mid 11: RT620/625 @ 125 MHz, on-chip FPU
cpu3: 512K byte write-back, 32 bytes/line, sw flush: cache enabled
=============================

=============================
NetBSD 2.0_BETA (PAULINA-SS20.MP) #0: Tue Sep  7 20:40:34 BST 2004
        
tim@felicity.flibble.org:/usr/obj/sys/arch/sparc/compile/PAULINA- 
SS20.MP

mainbus0 (root): SUNW,SPARCstation-20: hostid 72832b61
cpu0 at mainbus0: mid 8: RT620/625 @ 125 MHz, on-chip FPU
cpu0: 512K byte write-back, 32 bytes/line, sw flush: cache enabled
cpu1 at mainbus0: mid 9: RT620/625 @ 125 MHz, on-chip FPU
cpu1: 512K byte write-back, 32 bytes/line, sw flush: cache enabled
cpu2 at mainbus0: mid 10: RT620/625 @ 125 MHz, on-chip FPU
cpu2: 256K byte write-back, 64 bytes/line, sw flush: cache enabled
cpu3 at mainbus0: mid 11: RT620/625 @ 125 MHz, on-chip FPU
cpu3: 256K byte write-back, 64 bytes/line, sw flush: cache enabled
=============================

I did have a quick look at the code in /sys/arch/sparc/sparc/cpu.c, but  
couldn't really figure out what was going on =(

I appreciate that this is a fairly minor matter and that my config is  
basically unsupported, but I thought it might be worth mentioning...

-- 
Written on my iBook - It's BSD!