Subject: Re: SS20/MP Watchdog Reset
To: None <port-sparc@NetBSD.org>
From: Paul Kranenburg <pk@cs.few.eur.nl>
List: port-sparc
Date: 06/17/2004 15:16:07
> Watchdog resets are caused by taking a trap when traps are disabled.
>
> This particular fault is a level 15 interrupt. I think the only
> cause of level 15 interrupts are asynchronous memory errors.
> Since traps should only be disabled inside trap handlers, you
> are probably suffering from bad RAM.
A level 15 interrupt is also sent to all modules if one them resets,
whatever the reason.
With some luck, you might still get a stack trace of the reset CPU
by doing
ok <n> switch-cpu
ok ctrace
from the prom.
-pk