Subject: Re: CVS commit: src/sys/arch/sparc/sparc
To: None <port-sparc@netbsd.org>
From: Matt Dainty <matt@bodgit-n-scarper.com>
List: port-sparc
Date: 04/17/2004 20:56:16
On Thu, 2004-04-15 at 01:48, Steve Rumble wrote:
> On Wed, Apr 14, 2004 at 07:17:51PM +1000, matthew green wrote:
> > at this point any testing you can do will be greatly appreciated!
> 
> My SS20 dual hypersparc 180/150 died building userland with make
> -j 4. I was able to serial break into the prom, but upon resuming
> it locked hard and refuses to respond to further breaks.

I'm completely stabbing a guess here, but would the difference in L2
caches between 180 & 150MHz HyperSparc's cause any problems? Apparently
180 & 200MHz parts only run half-speed L2 caches according to
mbus.sunhelp.org/modules/index.htm#hyper whereas anything <= 166MHz is
full-speed. No idea if that sort've thing would make any difference.

Matt