Subject: re: hypersparc smp tailspin
To: Christopher SEKIYA <>
From: matthew green <>
List: port-sparc
Date: 02/09/2003 11:12:20
   On Sat, Feb 08, 2003 at 11:22:46PM +1100, matthew green wrote:
   > FWIW: this is what i see with brett's patch as well.
   I was seeing this with your patch as well :)

   (well, same behaviour -- didn't add in DEBUG and DIAGNOSTIC until I tried
   Brett's diff.  Shall I try again with yours?  Does your hypersparc spawn
   init properly with your i-cache disable code?)

with the icache disabled, my 4x 100mhz SS10 is a stable as the ss20/712
with 2 supersparc cpus... i haven't seen anything else broken there.