Subject: Re: SMP success
To: matthew green <mrg@eterna.com.au>
From: Hauke Fath <hauke@Espresso.Rhein-Neckar.DE>
List: port-sparc
Date: 01/05/2003 23:03:19
At 22:51 Uhr +1100 5.1.2003, matthew green wrote:
>due largely to the efforts of paul kranenburg, SMP support on sparc has
>finally arrived.  this has only been tested successfully so far on an
>ss20/712, an sun4/690 and an ss10/712 (i think), with a failure on a
>4/670.

Cool. Just when I started to think about putting the second CPU back on the
shelf... But, on my ss10 (2x SM71) I get

<#0> ok boot netbsd.new
Boot device: /iommu/sbus/espdma/esp/sd@0,0:a  File and args: netbsd.new
>> NetBSD/sparc Secondary Boot, Revision 1.12
>> (autobuild@tgm.daemon.org, Mon Sep  9 08:12:32 UTC 2002)
Booting netbsd.new
2273204+78392+305384 [143920+108745]=0x2d67c0
OBP version 3, revision 2.25 (plugin rev 2)
[ using 253160 bytes of netbsd ELF symbol table ]
Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
    The NetBSD Foundation, Inc.  All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
    The Regents of the University of California.  All rights reserved.

NetBSD 1.6L (PIZZA) #3: Sun Jan  5 22:55:33 CET 2003
    hauke@pizza.causeuse.org:/var/obj/sys/arch/sparc/compile/PIZZA
total memory = 319 MB
avail memory = 261 MB
using 896 buffers containing 48000 KB of memory
bootpath: /iommu@f,e0000000/sbus@f,e0001000/espdma@f,400000/esp@f,800000/sd@0,0
mainbus0 (root): SUNW,SPARCstation-10
cpu0 at mainbus0: mid 8: TMS390Z50 v0 or TMS390Z55 @ 75 MHz, on-chip FPU
cpu0: physical 20K instruction (64 b/l), 16K data (32 b/l), 1024K external
(32 b
/l): cache enabled
cpu1 at mainbus0: mid 10: TMS390Z50 v0 or TMS390Z55 @ 75 MHz, on-chip FPU
cpu1: physical 20K instruction (64 b/l), 16K data (32 b/l), 1024K external
(32 b
/l): cache enabled
obio0 at mainbus0
clock0 at obio0 slot 0 offset 0x200000: mk48t08: hostid 727021dd
timer0 at obio0 slot 0 offset 0x300000: delay constant 35
zs0 at obio0 slot 0 offset 0x100000 level 12 softpri 6
zstty0 at zs0 channel 0 (console i/o)
zstty1 at zs0 channel 1
zs1 at obio0 slot 0 offset 0x0 level 12 softpri 6
kbd0 at zs1 channel 0: baud rate 1200
ms0 at zs1 channel 1: baud rate 1200
fdc0 at obio0 slot 0 offset 0x700000 level 11
Watchdog Reset
<#0>

-- any ideas?

	hauke


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