Subject: CPU_IS* simplification
To: None <port-sparc@netbsd.org>
From: Jason R Thorpe <thorpej@wasabisystems.com>
List: port-sparc
Date: 07/16/2002 21:50:34
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Hi folks...
I'm going to check in the following patch. The CPU_ISSUN4OR4C
macros and the like are not really necessary, since in the case
where they expand to a constant, the compiler would still be able
to optimize if expressed as (CPU_ISSUN4 || CPU_ISSUN4C), like so:
(1 || 0)
(1 || 1)
(0 || 0)
(1 || cputyp == CPU_SUN4C)
etc.
Anyway, doing this simplifies adding CPU_ISSUN4D (which I am currently
working on).
--
-- Jason R. Thorpe <thorpej@wasabisystems.com>
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Index: dev/zs_kgdb.c
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/sparc/dev/zs_kgdb.c,v
retrieving revision 1.8
diff -u -r1.8 zs_kgdb.c
--- dev/zs_kgdb.c 2001/09/26 20:53:06 1.8
+++ dev/zs_kgdb.c 2002/07/17 04:44:29
@@ -352,7 +352,7 @@
#endif
#if defined(SUN4C) || defined(SUN4M)
- if (CPU_ISSUN4COR4M) {
+ if (CPU_ISSUN4C || CPU_ISSUN4M) {
int node;
node = firstchild(findroot());
Index: include/param.h
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/sparc/include/param.h,v
retrieving revision 1.52
diff -u -r1.52 param.h
--- include/param.h 2002/07/17 02:43:43 1.52
+++ include/param.h 2002/07/17 04:44:30
@@ -211,13 +211,10 @@
* extra memory references they'll generate.
*/
#define CPU_ISSUN4U (0)
-#define CPU_ISSUN4MOR4U (CPU_ISSUN4M)
#if defined(SUN4M) && defined(SUN4C) && defined(SUN4)
# define CPU_ISSUN4M (cputyp == CPU_SUN4M)
# define CPU_ISSUN4C (cputyp == CPU_SUN4C)
# define CPU_ISSUN4 (cputyp == CPU_SUN4)
-# define CPU_ISSUN4OR4C (cputyp == CPU_SUN4 || cputyp == CPU_SUN4C)
-# define CPU_ISSUN4COR4M (cputyp == CPU_SUN4C || cputyp == CPU_SUN4M)
# define NBPG nbpg
# define PGOFSET pgofset
# define PGSHIFT pgshift
@@ -225,8 +222,6 @@
# define CPU_ISSUN4M (cputyp == CPU_SUN4M)
# define CPU_ISSUN4C (cputyp == CPU_SUN4C)
# define CPU_ISSUN4 (0)
-# define CPU_ISSUN4OR4C (cputyp == CPU_SUN4C)
-# define CPU_ISSUN4COR4M (cputyp == CPU_SUN4C || cputyp == CPU_SUN4M)
# define NBPG 4096
# define PGOFSET (NBPG-1)
# define PGSHIFT SUN4CM_PGSHIFT
@@ -234,8 +229,6 @@
# define CPU_ISSUN4M (cputyp == CPU_SUN4M)
# define CPU_ISSUN4C (0)
# define CPU_ISSUN4 (cputyp == CPU_SUN4)
-# define CPU_ISSUN4OR4C (cputyp == CPU_SUN4)
-# define CPU_ISSUN4COR4M (cputyp == CPU_SUN4M)
# define NBPG nbpg
# define PGOFSET pgofset
# define PGSHIFT pgshift
@@ -243,8 +236,6 @@
# define CPU_ISSUN4M (1)
# define CPU_ISSUN4C (0)
# define CPU_ISSUN4 (0)
-# define CPU_ISSUN4OR4C (0)
-# define CPU_ISSUN4COR4M (1)
# define NBPG 4096
# define PGOFSET (NBPG-1)
# define PGSHIFT SUN4CM_PGSHIFT
@@ -252,8 +243,6 @@
# define CPU_ISSUN4M (0)
# define CPU_ISSUN4C (cputyp == CPU_SUN4C)
# define CPU_ISSUN4 (cputyp == CPU_SUN4)
-# define CPU_ISSUN4OR4C (1)
-# define CPU_ISSUN4COR4M (cputyp == CPU_SUN4C)
# define NBPG nbpg
# define PGOFSET pgofset
# define PGSHIFT pgshift
@@ -261,8 +250,6 @@
# define CPU_ISSUN4M (0)
# define CPU_ISSUN4C (1)
# define CPU_ISSUN4 (0)
-# define CPU_ISSUN4OR4C (1)
-# define CPU_ISSUN4COR4M (1)
# define NBPG 4096
# define PGOFSET (NBPG-1)
# define PGSHIFT SUN4CM_PGSHIFT
@@ -270,8 +257,6 @@
# define CPU_ISSUN4M (0)
# define CPU_ISSUN4C (0)
# define CPU_ISSUN4 (1)
-# define CPU_ISSUN4OR4C (1)
-# define CPU_ISSUN4COR4M (0)
# define NBPG 8192
# define PGOFSET (NBPG-1)
# define PGSHIFT SUN4_PGSHIFT
@@ -279,8 +264,6 @@
# define CPU_ISSUN4M (cputyp == CPU_SUN4M)
# define CPU_ISSUN4C (cputyp == CPU_SUN4C)
# define CPU_ISSUN4 (cputyp == CPU_SUN4)
-# define CPU_ISSUN4OR4C (cputyp == CPU_SUN4 || cputyp == CPU_SUN4C)
-# define CPU_ISSUN4COR4M (cputyp == CPU_SUN4C || cputyp == CPU_SUN4M)
# define NBPG nbpg
# define PGOFSET pgofset
# define PGSHIFT pgshift
Index: sparc/autoconf.c
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/sparc/sparc/autoconf.c,v
retrieving revision 1.169
diff -u -r1.169 autoconf.c
--- sparc/autoconf.c 2002/06/21 14:38:36 1.169
+++ sparc/autoconf.c 2002/07/17 04:44:32
@@ -302,7 +302,7 @@
#endif /* SUN4M */
#if defined(SUN4) || defined(SUN4C)
- if (CPU_ISSUN4OR4C) {
+ if (CPU_ISSUN4 || CPU_ISSUN4C) {
/* Map Interrupt Enable Register */
pmap_kenter_pa(INTRREG_VA,
INT_ENABLE_REG_PHYSADR | PMAP_NC | PMAP_OBIO,
@@ -940,7 +940,7 @@
#endif /* SUN4M */
#if defined(SUN4) || defined(SUN4C)
- if (CPU_ISSUN4OR4C)
+ if (CPU_ISSUN4 || CPU_ISSUN4C)
ienab_bis(IE_ALLIE);
#endif
Index: sparc/iommu.c
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/sparc/sparc/iommu.c,v
retrieving revision 1.64
diff -u -r1.64 iommu.c
--- sparc/iommu.c 2002/06/02 14:44:39 1.64
+++ sparc/iommu.c 2002/07/17 04:44:32
@@ -156,7 +156,7 @@
{
struct mainbus_attach_args *ma = aux;
- if (CPU_ISSUN4OR4C)
+ if (CPU_ISSUN4 || CPU_ISSUN4C)
return (0);
return (strcmp(cf->cf_driver->cd_name, ma->ma_name) == 0);
}
Index: sparc/machdep.c
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/sparc/sparc/machdep.c,v
retrieving revision 1.195
diff -u -r1.195 machdep.c
--- sparc/machdep.c 2002/07/04 23:32:06 1.195
+++ sparc/machdep.c 2002/07/17 04:44:34
@@ -336,7 +336,7 @@
exec_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr,
16*NCARGS, VM_MAP_PAGEABLE, FALSE, NULL);
- if (CPU_ISSUN4OR4C) {
+ if (CPU_ISSUN4 || CPU_ISSUN4C) {
/*
* Allocate dma map for 24-bit devices (le, ie)
* [dvma_base - dvma_end] is for VME devices..
Index: sparc/pmap.c
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/sparc/sparc/pmap.c,v
retrieving revision 1.208
diff -u -r1.208 pmap.c
--- sparc/pmap.c 2002/06/02 14:44:39 1.208
+++ sparc/pmap.c 2002/07/17 04:44:39
@@ -956,14 +956,14 @@
#define CTX_USABLE(pm,rp) ((pm)->pm_ctx != NULL )
#endif
-#define GAP_WIDEN(pm,vr) do if (CPU_ISSUN4OR4C) { \
- if (vr + 1 == pm->pm_gap_start) \
- pm->pm_gap_start = vr; \
- if (vr == pm->pm_gap_end) \
- pm->pm_gap_end = vr + 1; \
+#define GAP_WIDEN(pm,vr) do if (CPU_ISSUN4 || CPU_ISSUN4C) { \
+ if (vr + 1 == pm->pm_gap_start) \
+ pm->pm_gap_start = vr; \
+ if (vr == pm->pm_gap_end) \
+ pm->pm_gap_end = vr + 1; \
} while (0)
-#define GAP_SHRINK(pm,vr) do if (CPU_ISSUN4OR4C) { \
+#define GAP_SHRINK(pm,vr) do if (CPU_ISSUN4 || CPU_ISSUN4C) { \
int x; \
x = pm->pm_gap_start + (pm->pm_gap_end - pm->pm_gap_start) / 2; \
if (vr > x) { \
@@ -1950,7 +1950,7 @@
if (pmapdebug & PDB_CTX_ALLOC)
printf("ctx_alloc(%p)\n", pm);
#endif
- if (CPU_ISSUN4OR4C) {
+ if (CPU_ISSUN4 || CPU_ISSUN4C) {
gap_start = pm->pm_gap_start;
gap_end = pm->pm_gap_end;
}
@@ -1979,7 +1979,7 @@
#endif
c->c_pmap->pm_ctx = NULL;
doflush = (CACHEINFO.c_vactype != VAC_NONE);
- if (CPU_ISSUN4OR4C) {
+ if (CPU_ISSUN4 || CPU_ISSUN4C) {
if (gap_start < c->c_pmap->pm_gap_start)
gap_start = c->c_pmap->pm_gap_start;
if (gap_end > c->c_pmap->pm_gap_end)
@@ -1992,7 +1992,7 @@
pm->pm_ctx = c;
pm->pm_ctxnum = cnum;
- if (CPU_ISSUN4OR4C) {
+ if (CPU_ISSUN4 || CPU_ISSUN4C) {
/*
* Write pmap's region (3-level MMU) or segment table into
* the MMU.
@@ -2769,7 +2769,7 @@
pv_changepte4m(pv, 0, SRMMU_PG_C);
#endif
#if defined(SUN4) || defined(SUN4C)
- if (CPU_ISSUN4OR4C)
+ if (CPU_ISSUN4 || CPU_ISSUN4C)
pv_changepte4_4c(pv, PG_NC, 0);
#endif
}
@@ -2881,7 +2881,7 @@
#if defined(SUN4M)
pmap_bootstrap4m();
#endif
- } else if (CPU_ISSUN4OR4C) {
+ } else if (CPU_ISSUN4 || CPU_ISSUN4C) {
#if defined(SUN4) || defined(SUN4C)
pmap_bootstrap4_4c(nctx, nregion, nsegment);
#endif
@@ -3843,7 +3843,7 @@
{
int vs, vr;
- if (CPU_ISSUN4OR4C) {
+ if (CPU_ISSUN4 || CPU_ISSUN4C) {
#if defined(SUN4_MMU3L)
if (pm->pm_reglist.tqh_first)
panic("pmap_destroy: region list not empty");
@@ -3855,7 +3855,7 @@
for (vr = 0; vr < NUREG; vr++) {
struct regmap *rp = &pm->pm_regmap[vr];
- if (CPU_ISSUN4OR4C) {
+ if (CPU_ISSUN4 || CPU_ISSUN4C) {
#if defined(SUN4_MMU3L)
if (HASSUN4_MMU3L) {
if (rp->rg_smeg != reginval)
@@ -3923,7 +3923,7 @@
/* pm->pm_ctx = NULL; */
simple_lock_init(&pm->pm_lock);
- if (CPU_ISSUN4OR4C) {
+ if (CPU_ISSUN4 || CPU_ISSUN4C) {
TAILQ_INIT(&pm->pm_seglist);
#if defined(SUN4_MMU3L)
TAILQ_INIT(&pm->pm_reglist);
@@ -7369,7 +7369,7 @@
sz += npmemarr * sizeof(phys_ram_seg_t);
sz += sizeof(kernel_segmap_store);
- if (CPU_ISSUN4OR4C)
+ if (CPU_ISSUN4 || CPU_ISSUN4C)
/* For each pmeg in the MMU, we'll write NPTESG PTEs. */
sz += (seginval + 1) * NPTESG * sizeof(int);
@@ -7440,7 +7440,7 @@
kcpup->segmapoffset = segmapoffset =
memsegoffset + npmemarr * sizeof(phys_ram_seg_t);
- kcpup->npmeg = (CPU_ISSUN4OR4C) ? seginval + 1 : 0;
+ kcpup->npmeg = (CPU_ISSUN4 || CPU_ISSUN4C) ? seginval + 1 : 0;
kcpup->pmegoffset = pmegoffset =
segmapoffset + kcpup->nsegmap * sizeof(struct segmap);
Index: sparc/timer.c
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/sparc/sparc/timer.c,v
retrieving revision 1.4
diff -u -r1.4 timer.c
--- sparc/timer.c 2002/07/14 19:42:58 1.4
+++ sparc/timer.c 2002/07/17 04:44:40
@@ -378,7 +378,7 @@
printf(": delay constant %d\n", timerblurb);
#if defined(SUN4) || defined(SUN4C)
- if (CPU_ISSUN4OR4C) {
+ if (CPU_ISSUN4 || CPU_ISSUN4C) {
timer_init = timer_init_4;
level10.ih_fun = clockintr_4;
level14.ih_fun = statintr_4;
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