Hello Geoff!

  GB> Do you mean that the data is valid at the +ve clock transition
    > and (next byte) at the -ve transition? OK I know that the data
    > is NRZ so I suppose that this is practical, just requires a
    > phase skew between clock & data :-)

Surely there's always going to be one (so the data lines are settled
before they're clocked into the destination), DTC just uses both edges
for separate sets of data (I think). It's a technique that seems to be
cropping up in a number of places (VMEbus etc).

  GB> That's what cache's are for :-)

To some extent yes, but the read caches can only fill as quickly as
data can fly under the head.

  GB> Can you imagine what such signals do to the RF spectrum :-(

Sadly yes - (73 DE KB9YLW ;-)

Regards,
  - Andy Ball.