Subject: Re: Cache Chip Bug
To: Anthony DeLorenzo <gonzo@vex.net>
From: Rick Kelly <rmk@toad.rmkhome.com>
List: port-sparc
Date: 07/07/2000 01:33:56
Anthony DeLorenzo said:
>Searching the archives revealed this output in a few dmesg dumps, so I'm
>assuming that this is normal, but nevertheless.... My SS2 w/PowerUp
>reports this when it boots:
>
>cpu0 at mainbus0: cache chip bug; trap page uncached: W8601/8701 or
>MB86903 @ 40Mhz, on-chip FPU
This is from my SS2 with standard processor, 64 megs. etc...
mainbus0 (root): SUNW,Sun 4/75
cpu0 at mainbus0: cache chip bug; trap page uncached: CY7C601 @ 40 MHz, TMS390C6
02A FPU
cpu0: 64K byte write-through, 32 bytes/line, hw flush: cache enabled
It's normal. The box is as solid as a rock.
This particular box is the "Big Brother" server for my network. It hits
2.8-4.0 load average when doing CGI stuff to update the Big Brother pages.
It's running:
NetBSD seahag 1.4.1 NetBSD 1.4.1 (SEAHAG) #1: Sat Mar 4 00:05:04 MST 2000
rmk@seahag:/usr/src/sys/arch/sparc/compile/SEAHAG sparc
And it just keeps grinding along...
--
Rick Kelly rmk@rmkhome.com www.rmkhome.com