On Mon, Jun 26, 2000 at 12:26:13AM +0000, Craig Dewick wrote:
> 
> 
> As for CPU modules, you can use SM-41 up to SM-61 Supersparc CPU's, but not
> the SM-71 or SM-81 SuperSparc-2 CPU's (they were never supported on the
> 4/6x0's from what I have gleaned out of Sun's documentation at
> docs.sun.com).

The SM71 & SM81 modules have a different MXCC cache controller chip.  It has 
slightly different timing requirements, which the 600MP's Mbus apparently
doesn't meet.  If you have an FE guide, you'll notice that all the 600MP 
supported modules have MXCC 2.x, where later modules are MXCC 3.x.  This 
transition appears to have occured during the SM61 module production.  I know
I've configured MXCC 3.x SM61's in a 600MP board though.  So I don't know 
that the SM71's and 81's will fail for that reason alone.  Has anyone here
tried it?  I know the SS10 required a prom upgarde to support the SM71's, I 
wonder if it's something that could be compensated for in the NetBSD kernel.


> I don't know how the Hypersparc support goes, but Ross
> probably had special bootROM's which could support most of the high-end
> modules right up to the 125 or 150 Mhz ones. Maybe if someone from
> Bridgepoint reads this they can give us some more accurate info about
> Hypersparc support in 4/6x0 bootROM's? 8-)
> 


I've only seen one Ross upgrade kit for a 600MP.  It was for the dual 100Mhz 
mods, and it contained 4 EEPROM replacements for the boot prom.  It would be 
nice to get images of those released and archived. :-)

Cheers,

Rob