Hi,

the DBRI chip uses a circular "interrupt buffer" -- a
block of 64 32-bit words in main memory -- for recording
events which caused an interrupt. Each time an interrupt
is signalled, the chip has written one or more 32-bit
words to this buffer (usually not more than three per
interrupt).

The interrupt handler reads (and processes) these interrupt
words one by one until it reads a 0. After reading an
interrupt word, it overwrites it with 0.

Before reading from the interrupt buffer bus_dmamap_sync()
is called with BUS_DMASYNC_POSTREAD (and after writing the
0 words, BUS_DMASYNC_PREREAD). Unfortunately, the handler
has no knowledge in advance of how many 32-bit words are
to be read, so there are (at least) two variants to sync
the buffer:

1) call bus_dmamap_sync(BUS_DMASYNC_POSTREAD) for each
   32-bit word just before it is read by the handler
   (i.e. up to, say, three times per interrupt)

2) call bus_dmamap_sync(BUS_DMASYNC_POSTREAD) for the
   whole buffer (64 32-bit words) once at the beginning
   of the handler

How expensive is a bus_dmamap_sync() call? At the moment,
I'd prefer the first variant, but if there is a large cost
for each bus_dmamap_sync() call independent of the size of
the corresponding memory area, I am convinced to use the
second one.

    Ingolf
-- 

Ingolf Koch     ICQ#60829470     Beste Kneipe in Jena-Ost
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