der Mouse  <mouse@Rodents.Montreal.QC.CA> writes:

> > Both power and 68k macs use a 3.68 MHz receive clock (14400 * 256).
> > So from the BRG, the highest baud rate is 14400*256/16/4 = 57600.
> 
> Only if you insist on using the BRG in divide-by-16 mode.  Use
> divide-by-1 instead and your max rate is 14400*256/4 = 921600, just as
> the SPARC's max rate in divide-by-1 mode is 1228800 (= 9600*512/4).

I believe I see the source of your confusion now.

The 16x divisor is *not a property of the BRG*.  It is a property of
the transmit/receive stages, which are entirely separate.  Primarily,
it controls the number of receive samples taken in each bit slot to
detect state transitions.

It is absolutely critical in asynchronous modes (that is, modes with
no clock coupling between the two machines/devices) to use a divisor
of at least 4x.  Otherwise the sampling will not be stable due to
clock drift, and you *will* get corrupted data.  I know there is a
passage or three in the z8530 manual about this (but I'm on a text
display right now and can't look it up).

In short, what you're doing will not work reliably -- if at all -- and
should not be supported.

That said, it may be possible with genuine serial chips (either the
Zilog variety or a clone chip, but probably not what's integrated into
the Super-I/O chips on later machines) to tie a faster crystal between
two pins and use it as an external clock source.  I had intended to
try this at some point, but I still don't have any SPARCs I can hack.