Subject: Re: High serial port (output) speeds
To: der Mouse , Jukka Marin <>
From: Bill Studenmund <>
List: port-sparc
Date: 10/22/1999 12:13:03
On Fri, 22 Oct 1999, Jukka Marin wrote:

> On Thu, Oct 21, 1999 at 11:20:26PM -0400, der Mouse wrote:
> > I think I know why the zs chips are normally run with a X16 clock
> > divisor.  But is there any reason why they shouldn't run X1 if userland
> > requests a baudrate that can be achieved that way but not with X16?

Yes, because if you aren't sync'd to an external clock source, it's

> Many UART chips use the 16x clock to sample the RxD pin multiple times
> for every bit, then they use a majority algorithm to determine the final
> state of the bit (in case all samples don't agree).  I don't know if
> this is what the zs chip is doing with the 16x clock - probably yes.

In other than 1x mode, the chip will detect the start of a transmission,
and then sample the bits at the middle of the bit cell.

What I think/hope it does in 1x mode is change transmission state on one
edge, and detect on the other.

The problem if you aren't using an external clock is that if the 1x clocks
line up right, the receiver is sampling right when the transmitter is
changing from one bit to another. I know of no reliable way to catch this.

Unfortunatly I don't think SUN wired PCLK to either RTxC or TRxC. If they
had, you could do direct 16x or 32x (which would give you two higher baud
rates for free).

> In a quiet environment with good cables and UARTs and transceivers it
> shouldn't really matter - but if there's noise and/or voltage spikes,
> you'll get transmission errors easier with the 1x sampling method
> (although I have used it successfully when creating bit-banged serial
> ports).


Take care,