On Sat, 30 Jan 1999, Matthew Jacob wrote:

> Yes, somebody else mentioned bypassing the MMU. Now, I'm far from
> knowledgeable of recent Sun internal hardware but does the ASI also bypass
> any buffered write hardware? It used to be part of the Comet axioms that
> you could have an arbitrary number of write buffers between a CPU and the
> device and that you wouldn't necessarily stall until you tried to read the
> same location.

We're comparing a write to a virtual address that's mapped with the
sideffect bit set in the TTE to a write to an explicit physical address
bypassing all caches.  My interpretation of the _UltraSPARC_User's_Manual_
is that all writes go to the store buffer so once it gets beyond the MMU
all stores are treated the same way.  OTOH, if the CPU is not operating in
the TSO memory model or is trying to access one of the internal ASIs then
memory barrier instructions are needed to keep things sane.  This means
that even if you write to a device you won't necessarily stall even if you
tried to read the same location, you'll just get back the value that's in
the write buffer.

=========================================================================
Eduardo Horvath				eeh@one-o.com
	"I need to find a pithy new quote." -- me