Subject: Re: 2nd CPU in SS10 - the saga continues
To: Hubert Feyrer <feyrer@rfhs8012.fh-regensburg.de>
From: Rob Vassar <rvassar@value.net>
List: port-sparc
Date: 11/26/1998 07:25:11
> 
> I'm still unsure what this 1x390Z50/55 days - is this the clock rate of
> the CPU?

These are the quantity and part numbers of the chips coupled to the
Mbus.  390Z50 is the TI part number for the early SuperSPARC CPU. 
390Z55 is the part number for the MXCC, or MBus/XBus Cache Controller. 
When you run the SM40 module, you'll see 390Z50, as that is the chip
presented to the Mbus.  When running the SM41 module, you'll see
390Z55.  The 390Z50 is still there, but not exposed to the Mbus.

Sun shipped 7 different SM4x Mbus modules.  Breakdown as follows:
501-2219 - SM40, SuperSPARC 2.x, does not support MP.
501-2358 - SM40, SuperSPARC 3.x, MP with OBP 2.12 but not recommended.
501-2570 - SM40, SuperSPARC 3.x, MP with OBP 2.12.
501-2258 - SM41, MXCC 1.x, SuperSPARC 2.x. MP works fine.
501-2270 - SM41, MXCC 1.x or 2.x, SuperSPARC 2.x, MP works fine.
501-2318 - SM41, MXCC 1.x, SuperSPARC 2.x.  This is an early SC2000
module.
501-2359 - SM41, MXCC 1.x, SuperSPARC 2.x. MP works fine.

-Rob
rvassar@value.net

> 
>  - Hubert
> 
> --
> Hubert Feyrer <hubert.feyrer@rz.uni-regensburg.de>