der Mouse wrote:
>As far as I know your dim recollection is incorrect, and SPARCs are
>always big-endian.  The MIPS processor may be what you're thinking of;
>that I do believe can be run either way (though I don't know if any
>hardware exists that can switch from software).

SPARCs are indeed bigendian; I believe that the V9 architecture provides
instructions for accessing little-endian data, though. [haven't got access
to a copy of the architecture manual currently :-< ] ISTR Alphae can run in
both ways, possibly allowing cunning hackery with executing the same code
in either mode :->

>> On a similar note, do I need to be concerned about alignment of
>> structures?
>
>Maybe.  On the SPARC, basically everything needs to be aligned on a
>"natural" boundary (ie, every primitive should be aligned to a multiple
>of its size).  The compiler normally takes care of this, but if the
>code starts playing games with pointer arithmetic it can break.

OTOH, there is a specific trap for unaligned memory access, so it is possible
for the kernel to emulate the instruction; efficiency goes out the window, of
course. <fx: checks kernel source> Yes, NetBSD does do this, see
arch/sparc/sparc/emul.c: fixalign(). It appears at first glance to be
something you have to explicitly enable, though.

Peter Maydell