Subject: Final couple of bits regarding the TurboSPARC
To: None <port-sparc@NetBSD.ORG>
From: Greg Earle <earle@isolar.Tujunga.CA.US>
Date: 07/02/1997 21:55:50
I stumbled upon an interesting TurboSPARC FAQ. It's mostly for hardware
types but I thought these entries were of interest. Full details at
if anyone's interested.
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TurboSPARC can be configured to boot in the same way as a MicroSPARC II,
i.e. from SBus (VA[31:00]=0x70000000, PA[27:00]=0x0000000). What type of
SBus read transaction does the TurboSPARC issue when fetching
instructions from this address ?
VA=0X70000000 = SBus Slot 4/ Boot PROM in the memory map. During
boot-up the processor typically requests for double word. The SBus controller
handles this request by word transaction. Depending on how the slave
responds, bus sizing can take place at which case byte transaction will occur.
What Cache RAMs will Fujitsu use on the 200MHz TurboSPARC module in
order to run a 100MHz IO clock ?
Ans: 10ns cycle time, 5V tolerant, linear pipeline burst SRAM. 200MHz =
10ns so 12ns cycle time SRAM could no longer be used. Refer to SRAM app notes
entitled:" System Design Guidelines for TurboSPARC L2 cache" for more info.
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P.S. My little birdy confirmed that the 200 MHz machine was "too fast" as in
"too fast" relative to the then-extant Ultra-1/140. I think this is a
specious argument (since when is a 165 SPECint92 machine a threat to a
215 SPECint92 machine?), but I'm a techie and not a marketeer ... :-)