> Correct me if I'm wrong, but does the sparc processor really have a
> stack in hardware?  I thought that it saves all the machine state at
> the time of the trap in onchip registers and restarts at some known
> location.  OK, it might get a "double" trap when it cannot access the
> trap handling code, but I don't think that it can get one when
> accessing something on the (software implemented) stack.

It almost can.

When the CPU takes a trap, it may shift into an otherwise invalid
register window (the "trap window"); it's true this is all the CPU
really does.

A double error halt ("Watchdog reset!" on machines with older ROMs) is
what happens when the machine takes a trap while traps are disabled.
When a trap is taken, traps are automatically disabled; if another trap
occurs before the trap handler re-enables traps, this is what happens.
(If the kernel stack is invalid, this is probably what will happen; the
machine will take an MMU-provoked trap while trying to spill register
windows to the stack.  It might be avoidable, but it's not at all clear
to me how.)

					der Mouse

			       mouse@rodents.montreal.qc.ca
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