> On Wed, 16 Oct 1996 22:57:04 -0400 
>  Aaron Brown <abrown@eecs.harvard.edu> wrote:
> 
>  > Does your SS10 have a SuperSPARC processor? Does it have a "MXCC" (1-MB
>  > level-2 "ecache")? If it is a hypersparc, it won't work. If it is a super-
>  > sparc without a MXCC, it also won't work under NetBSD-1.2 unless you add
>  > a hack to the kernel to disable the cache...[perhaps this should go into
>  > the first 1.2 patch...]
> 
> I have such a hack in my local tree ... since I have one of the pesky
> lame SS10s :-)
> 
> Aaron: want me to just commit it?  The option is called
> "SUN4M_NO_CACHE_ENABLE".  It does the obvious thing :-)

Actually, it is possible to auto-detect these things by one of the mbus bits
(look at how the -current code decides whether to uncache page tables).
I'm not sure when the patch is going out, but if you can wait a week or so
I think I can munge the autodetection to work. (I can't do it now since
I'm struggling against the Sigmetrics deadline)...

If you want to commit the option in the meantime, feel free...

--Aaron