[ re-directing to port-sparc ... that's where it belongs, really... ]

On Wed, 25 Sep 1996 03:57:14 +0200 (MET DST) 
 Koen De Vleeschauwer <koen@EU.net> wrote:

 > When trying to boot -current on a Sun SS10:
 > cpu0 at mainbus0: TI, TMS390Z50 @ 36 Mhz, on-chip FPU
 > cpu0: physical 20K instruction (64b/l), 16K data (32b/l) cache enabled
 > then hangs; no response to break.

This is the same problem I have with the SS10 in my network lab.

Having talked to Aaron Brown and Chris Torek a bit about it, it turns
out that the CPU module in my SS10 doesn't have the MXCC stuff, and thus
doing the cache operations is _much_ harrier...  Apparently, one model
of SS20 is the same way.

I dunno if Aaron's figured out a way to deal with that yet...

short answer, until this problem gets fixed, your SS10 will lose once
the cache is enabled... I've built a kernel with a local hack that
avoids the cache enable on this particular system ... so I can at least
boot, but it's _s__l__o__w_ :-)

Jason R. Thorpe                                       thorpej@nas.nasa.gov
NASA Ames Research Center                               Home: 408.866.1912
NAS: M/S 258-6                                          Work: 415.604.0935
Moffett Field, CA 94035                                Pager: 415.428.6939