Hi all,

I've been working on rewriting the Sparc CPU identification code as a first 
step in cleaning up a lot of the crufty code that results from differences 
between CPU models in each of the Sparc families. This work is also needed if 
we ever make it to multiprocessor NetBSD.

I've got a test kernel that implements my first whack at these changes, and 
since the changes affect the Sun4, Sun4c, and Sun4m, I need people to try it 
out and see if it boots (I only have an SS20 to test it on, and I had to guess 
at a lot of the sun4/sun4c details).

For those of you with SS4s and SS5s, the code should now (theoretically) 
support the microsparc-2 caches, but no guarantees. For those of you getting 
panics about 36-bit iospaces on microsparcs, this kernel will provide more 
diagnostic information to help me find the bug.

I'd appreciate it if anyone could try booting this kernel on various machines 
and letting me know if it works. It is a GENERIC 1.2A kernel.

Please note, however, that there are absolutely no guarantees that it will 
work at all...standard disclaimers apply.

Find it at:

ftp://rioja.eecs.harvard.edu/pub/abrown/netbsd_cpusoftc.gz

Thanks!

--Aaron