Hi all,

Sorry for not responding to any of the bug reports sooner, but I've been
tied up with exams and final projects for the past two weeks, and have
barely had a chance to read email.  Unfortunately, this also means I
haven't had a chance to do much with the 4m code recently. 

But anyway, I've been reading and filing all the bug reports, and there 
seems to be a few big problems with some hardware:
	* microsparc2 (SS5) support is clearly broken. I've figured out
	  that this is because for some reason the ms2 MMU has the same
	  implementation code as the supersparc MMU, even though the
	  MMUs are not the same! :-P I'll have to put in some other means
	  of testing which MMU type is present.

	* Caches and CPU speeds aren't getting detected on some machines.
	  This is probably due to differences in the OpenPROM layout
	  on these machines. The SS20 has its CPUs as children of the
	  root node on the OpenPROM; each CPU node has properties 
	  describing caches and cpu speed, etc. I'd appreciate it if
	  someone with an SS5 or other machine which doesn't work
	  could do a ls of their PROM's root node, and then do a 
	  ".attributes" of the root node and of any nodes which
	  look like CPUs, and then send me the output.

	* There are a few more bizarre bugs, like the SS10 problem which
	  doesn't seem to have a rational explanation.

Also, for those who requested copies of the source tree, I'll be making 
copies available upon request within the next few days (I need to 
re-merge with -current first and update the copyrights in all the files). 
Because of my busy schedule, it does not look like there will be an 
official source release before USENIX; I'm guessing that it will be ready 
sometime in February.

--Aaron