In article <20051213124554.GB20118@rezrov.net>
wileyc@rezrov.net wrote:

> +	/* Workaround for non-coherent R10K systems */
> +	if (MIPS_PRID_IMPL(cpu_id) == MIPS_R10000)
> +		dma_start = 0x800000;

BTW, where does this 0x800000 come from?
Hardware (crime) limitation?
Or software boundary to store kernel into the lower 8MB region?

>  	if (nsegs == 1) {
> -		if (flags & BUS_DMA_COHERENT)
> +		if ( MIPS_PRID_IMPL(cpu_id) == MIPS_R10000 )
> +			*kvap = (caddr_t)MIPS_PHYS_TO_KSEG1(segs[0].ds_addr);
> +		else if (flags & BUS_DMA_COHERENT)
>  			*kvap = (caddr_t)MIPS_PHYS_TO_KSEG1(segs[0].ds_addr);
>  		else
>  			*kvap = (caddr_t)MIPS_PHYS_TO_KSEG0(segs[0].ds_addr);
>  		return 0;
>  	}

This is bus_dmamem_map(9). Only some DMA descriptors are handled
by this function. In bus_dmamap_load_buffer(), any KVA buffers
could be used for DMA ops unless you prepare the bounce buffer.

I'm not sure if only TLB flush is needed to avoid speculative store,
or removing mapping is needed, but if the former it could be done in
bus_dmamap_sync(9). If the latter, I have no idea of trivial workaround
other than bounce buffer.
---
Izumi Tsutsui