On Mon, Nov 24, 2003 at 10:21:05PM +0900, Christopher SEKIYA wrote:
> On Sun, Nov 23, 2003 at 06:06:15PM +0100, Vladimir Kotal wrote:
> 
> > cpu0 at mainbus0: MIPS R5000 CPU (0x2310) Rev. 1.0 with built-in FPU Rev. 1.0
> > cpu0: 32KB/32B 2-way set-associative L1 Instruction cache, 48 TLB entries
> > cpu0: 32KB/32B 2-way set-associative write-back L1 Data cache
> > imc0 at mainbus0 addr 0x1fa00000
> 
> -current doesn't because apparently your ARCS clears either the SC or SE
> bit in cop0.
> 

Ah.

> I'm going to send a test kernel to you tomorrow that, with luck, will let us
> know exactly what's going on here.  Your install failure was most likely a
> L2 cache botch.

Thanks. I've already installed full 20031120 snapshot and first thing I
tried to compile was bin/systrace -> another nice freeze while linking the
binary.


v.