Subject: O2 R10000 cache
To: None <port-sgimips@netbsd.org>
From: KIYOHARA Takashi <kiyohara@kk.iij4u.or.jp>
List: port-sgimips
Date: 08/23/2003 02:14:07
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Hi!
quick hack R10000 cache!
;)
----
> boot -f bootp():/netbsd
Setting $netaddr to 192.168.1.7 (from server )
Obtaining /netbsd from server
3041456+265372 entry: 0x80069000
[ Kernel symbol table missing! ]
CPU clock speed = 195.91Mhz*Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
The NetBSD Foundation, Inc. All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
The Regents of the University of California. All rights reserved.
NetBSD 1.6W (GENERIC) #1: Fri Aug 22 02:06:09 JST 2003
lance@highpriestess.fool:/sys/arch/sgimips/compile/GENERIC
192 MB memory, 167 MB free, 6848 KB for ARCS, 9932 KB in 2483 buffers
mainbus0 (root): SGI-IP32 [SGI, 7], 1 processor
cpu0 at mainbus0: MIPS R10000 CPU (0x927) Rev. 2.7 with built-in FPU Rev. 0.0
cpu0: 32KB/64B 2-way set-associative L1 Instruction cache, 64 TLB entries
cpu0: 32KB/32B 2-way set-associative write-back L1 Data cache
cpu0: 0KB/64B 2-way set-associative write-back L2 Data cache
crime0 at mainbus0 addr 0x14000000: rev 1.1 (CRIME_ID: a1)
mace0 at mainbus0 addr 0x1f000000: rev 1
com0 at mace0 offset 0x390000: ns16550a, working fifo
com0: console
com1 at mace0 offset 0x398000: ns16550a, working fifo
pckbc0 at mace0 offset 0x320000: stub
lpt0 at mace0 offset 0x380000: stub
mcclock0 at mace0 offset 0x3a0000
mec0 at mace0 offset 0x280000: MAC-110 Ethernet, rev 1
mec0: station address 08:00:69:02:ae:e7
mec0: sorry, this is not a real driver
nsphy0 at mec0 phy 8: DP83840 10/100 media interface, rev. 1
nsphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
macepci0 at mace0 offset 0x80000: rev 1
pci_addr_fixup: 000:03:0 0x1112 0x2200 new address 0x00003000 (size 0x100)
pci_addr_fixup: 000:03:0 0x1112 0x2200 new address 0x80100000 (size 0x100)
pci0 at macepci0 bus 0
pci0: i/o space, memory space enabled, rd/line, rd/mult, wr/inv ok
ahc0 at pci0 dev 1 function 0: unable to map registers
ahc1 at pci0 dev 2 function 0: unable to map registers
RNS 2200 FDDI (FDDI network, revision 0x03) at pci0 dev 3 function 0 not configured
biomask 07 netmask 07 ttymask 07 clockmask 87
boot device: <unknown>
root device: mec0
dump device:
file system (default generic):
root on mec0
nfs_boot: 'mec0' not found
no file system for mec0
cannot mount root, error = 79
root device (default mec0):
----
mec0: sorry, this is not a real driver
^^^^^^^^^^^^^^^^^
ahc0 at pci0 dev 1 function 0: unable to map registers
^^^^^^^^^^^^^^^^^^^^^^^
...
thanks
--
kiyohara
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diff -cr arch/mips/conf/files.mips /home/ax/union_src/sys/arch/mips/conf/files.mips
*** arch/mips/conf/files.mips Sat Mar 22 01:50:14 2003
--- /home/ax/union_src/sys/arch/mips/conf/files.mips Thu Aug 21 02:10:58 2003
***************
*** 47,52 ****
--- 47,53 ----
file arch/mips/mips/cache_r5k.c mips3 | mips4
file arch/mips/mips/cache_r5k_subr.S mips3 | mips4
file arch/mips/mips/cache_r5900.c mips3 & mips3_5900
+ file arch/mips/mips/cache_r10k.c mips3 | mips4
file arch/mips/mips/cache_mipsNN.c mips32 | mips64
file arch/mips/mips/in_cksum.c inet
diff -cr arch/mips/include/cache_r10k.h /home/ax/union_src/sys/arch/mips/include/cache_r10k.h
*** arch/mips/include/cache_r10k.h Sat Aug 23 01:45:43 2003
--- /home/ax/union_src/sys/arch/mips/include/cache_r10k.h Sat Aug 23 01:51:38 2003
***************
*** 0 ****
--- 1,127 ----
+ /* $NetBSD: $ */
+
+ /*
+ * Copyright (c) 2003 KIYOHARA Takashi <kiyohara@kk.iij4u.or.jp>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ /*
+ * Cache definitions/operations for R10000-style caches.
+ */
+
+ #define CACHEOP_R10K_CBARRIER (5 << 2) /* I */
+ #define CACHEOP_R10K_IDX_LOAD_DATA (6 << 2) /* I, D, SD */
+ #define CACHEOP_R10K_IDX_STORE_DATA (7 << 2) /* SI, SD */
+
+ #if defined(_KERNEL) && !defined(_LOCORE)
+
+ /*
+ * cache_r10k_op_8lines_64:
+ *
+ * Perform the specified cache operation on 8 64-byte cache lines.
+ */
+ #define cache_r10k_op_8lines_64(va, op) \
+ do { \
+ __asm __volatile( \
+ ".set noreorder \n\t" \
+ "cache %1, 0x000(%0); cache %1, 0x040(%0) \n\t" \
+ "cache %1, 0x080(%0); cache %1, 0x0c0(%0) \n\t" \
+ "cache %1, 0x100(%0); cache %1, 0x140(%0) \n\t" \
+ "cache %1, 0x180(%0); cache %1, 0x1c0(%0) \n\t" \
+ ".set reorder" \
+ : \
+ : "r" (va), "i" (op) \
+ : "memory"); \
+ } while (/*CONSTCOND*/0)
+
+ /*
+ * cache_r10k_op_32lines_64:
+ *
+ * Perform the specified cache operation on 32 64-byte
+ * cache lines.
+ */
+ #define cache_r10k_op_32lines_64(va, op) \
+ do { \
+ __asm __volatile( \
+ ".set noreorder \n\t" \
+ "cache %1, 0x000(%0); cache %1, 0x040(%0); \n\t" \
+ "cache %1, 0x080(%0); cache %1, 0x0c0(%0); \n\t" \
+ "cache %1, 0x100(%0); cache %1, 0x140(%0); \n\t" \
+ "cache %1, 0x180(%0); cache %1, 0x1c0(%0); \n\t" \
+ "cache %1, 0x200(%0); cache %1, 0x240(%0); \n\t" \
+ "cache %1, 0x280(%0); cache %1, 0x2c0(%0); \n\t" \
+ "cache %1, 0x300(%0); cache %1, 0x340(%0); \n\t" \
+ "cache %1, 0x380(%0); cache %1, 0x3c0(%0); \n\t" \
+ "cache %1, 0x400(%0); cache %1, 0x440(%0); \n\t" \
+ "cache %1, 0x480(%0); cache %1, 0x4c0(%0); \n\t" \
+ "cache %1, 0x500(%0); cache %1, 0x540(%0); \n\t" \
+ "cache %1, 0x580(%0); cache %1, 0x5c0(%0); \n\t" \
+ "cache %1, 0x600(%0); cache %1, 0x640(%0); \n\t" \
+ "cache %1, 0x680(%0); cache %1, 0x6c0(%0); \n\t" \
+ "cache %1, 0x700(%0); cache %1, 0x740(%0); \n\t" \
+ "cache %1, 0x780(%0); cache %1, 0x7c0(%0); \n\t" \
+ ".set reorder" \
+ : \
+ : "r" (va), "i" (op) \
+ : "memory"); \
+ } while (/*CONSTCOND*/0)
+
+ /*
+ * cache_r10k_op_16lines_32_2way:
+ *
+ * Perform the specified cache operation on 16 64-byte
+ * cache lines, 2-ways.
+ */
+ #define cache_r10k_op_16lines_64_2way(va1, va2, op) \
+ do { \
+ __asm __volatile( \
+ ".set noreorder \n\t" \
+ "cache %2, 0x000(%0); cache %2, 0x000(%1); \n\t" \
+ "cache %2, 0x040(%0); cache %2, 0x040(%1); \n\t" \
+ "cache %2, 0x080(%0); cache %2, 0x080(%1); \n\t" \
+ "cache %2, 0x0c0(%0); cache %2, 0x0c0(%1); \n\t" \
+ "cache %2, 0x100(%0); cache %2, 0x100(%1); \n\t" \
+ "cache %2, 0x140(%0); cache %2, 0x140(%1); \n\t" \
+ "cache %2, 0x180(%0); cache %2, 0x180(%1); \n\t" \
+ "cache %2, 0x1c0(%0); cache %2, 0x1c0(%1); \n\t" \
+ "cache %2, 0x200(%0); cache %2, 0x200(%1); \n\t" \
+ "cache %2, 0x240(%0); cache %2, 0x240(%1); \n\t" \
+ "cache %2, 0x280(%0); cache %2, 0x280(%1); \n\t" \
+ "cache %2, 0x2c0(%0); cache %2, 0x2c0(%1); \n\t" \
+ "cache %2, 0x300(%0); cache %2, 0x300(%1); \n\t" \
+ "cache %2, 0x340(%0); cache %2, 0x340(%1); \n\t" \
+ "cache %2, 0x380(%0); cache %2, 0x380(%1); \n\t" \
+ "cache %2, 0x3c0(%0); cache %2, 0x3c0(%1); \n\t" \
+ ".set reorder" \
+ : \
+ : "r" (va1), "r" (va2), "i" (op) \
+ : "memory"); \
+ } while (/*CONSTCOND*/0)
+
+ void r10k_icache_sync_all_64(void);
+ void r10k_icache_sync_range_64(vaddr_t, vsize_t);
+ void r10k_icache_sync_range_index_64(vaddr_t, vsize_t);
+
+ void r10k_pdcache_wb_range(vaddr_t, vsize_t);
+
+ #endif /* _KERNEL && !_LOCORE */
diff -cr arch/mips/include/cpuregs.h /home/ax/union_src/sys/arch/mips/include/cpuregs.h
*** arch/mips/include/cpuregs.h Fri Aug 8 23:44:56 2003
--- /home/ax/union_src/sys/arch/mips/include/cpuregs.h Thu Aug 21 02:15:33 2003
***************
*** 364,369 ****
--- 364,398 ----
#define MIPS3_CONFIG_CM 0x80000000
/*
+ * The bits in the MIPS4 config register.
+ */
+
+ /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
+ #define MIPS4_CONFIG_K0_MASK MIPS3_CONFIG_K0_MASK
+ #define MIPS4_CONFIG_DN_MASK 0x00000018 /* Device number */
+ #define MIPS4_CONFIG_CT 0x00000020 /* CohPrcReqTar */
+ #define MIPS4_CONFIG_PE 0x00000040 /* PreElmReq */
+ #define MIPS4_CONFIG_PM_MASK 0x00000180 /* PreReqMax */
+ #define MIPS4_CONFIG_EC_MASK 0x00001e00 /* SysClkDiv */
+ #define MIPS4_CONFIG_SB 0x00002000 /* SCBlkSize */
+ #define MIPS4_CONFIG_SK 0x00004000 /* SCColEn */
+ #define MIPS4_CONFIG_BE 0x00008000 /* MemEnd */
+ #define MIPS4_CONFIG_SS_MASK 0x00070000 /* SCSize */
+ #define MIPS4_CONFIG_SC_MASK 0x00380000 /* SCClkDiv */
+ #define MIPS4_CONFIG_RESERVED 0x03c00000 /* Reserved wired 0 */
+ #define MIPS4_CONFIG_DC_MASK 0x1c000000 /* Primary D-Cache size */
+ #define MIPS4_CONFIG_IC_MASK 0xe0000000 /* Primary I-Cache size */
+
+ #define MIPS4_CONFIG_DC_SHIFT 26
+ #define MIPS4_CONFIG_IC_SHIFT 29
+
+ #define MIPS4_CONFIG_CACHE_SIZE(config, mask, base, shift) \
+ ((base) << (((config) & (mask)) >> (shift)))
+
+ #define MIPS4_CONFIG_CACHE_L2_LSIZE(config) \
+ (((config) & MIPS4_CONFIG_SB) ? 128 : 64)
+
+ /*
* Location of exception vectors.
*
* Common vectors: reset and UTLB miss.
diff -cr arch/mips/mips/cache.c /home/ax/union_src/sys/arch/mips/mips/cache.c
*** arch/mips/mips/cache.c Fri Aug 1 23:12:38 2003
--- /home/ax/union_src/sys/arch/mips/mips/cache.c Fri Aug 22 00:26:11 2003
***************
*** 86,91 ****
--- 86,92 ----
#ifdef MIPS3_PLUS
#include <mips/cache_r4k.h>
#include <mips/cache_r5k.h>
+ #include <mips/cache_r10k.h>
#endif
#if defined(MIPS32) || defined(MIPS64)
***************
*** 164,169 ****
--- 165,171 ----
#include <mips/cache_r5900.h>
#endif /* MIPS3_5900 */
void mips3_get_cache_config(int);
+ void mips4_get_cache_config(int);
#endif /* MIPS3 || MIPS4 */
#if defined(MIPS1) || defined(MIPS3) || defined(MIPS4)
***************
*** 600,605 ****
--- 602,648 ----
r5900_pdcache_wb_range_64;
break;
#endif /* MIPS3_5900 */
+ case MIPS_R10000:
+ /* cache spec */
+ mips_picache_ways = 2;
+ mips_pdcache_ways = 2;
+ mips_sdcache_ways = 2;
+
+ mips4_get_cache_config(csizebase);
+
+ switch (mips_picache_line_size) {
+ case 64: /* 64 Byte */
+ mips_cache_ops.mco_icache_sync_all =
+ r10k_icache_sync_all_64;
+ mips_cache_ops.mco_icache_sync_range =
+ r10k_icache_sync_range_64;
+ mips_cache_ops.mco_icache_sync_range_index =
+ r10k_icache_sync_range_index_64;
+ break;
+
+ default:
+ panic("r10k picache line size %d",
+ mips_picache_line_size);
+ }
+ switch (mips_pdcache_line_size) {
+ case 32: /* 32 Byte */
+ mips_cache_ops.mco_pdcache_wbinv_all =
+ r5k_pdcache_wbinv_all_32;
+ mips_cache_ops.mco_pdcache_wbinv_range =
+ r5k_pdcache_wbinv_range_32;
+ mips_cache_ops.mco_pdcache_wbinv_range_index =
+ r5k_pdcache_wbinv_range_index_32;
+ mips_cache_ops.mco_pdcache_inv_range =
+ r5k_pdcache_inv_range_32;
+ mips_cache_ops.mco_pdcache_wb_range =
+ r10k_pdcache_wb_range;
+ break;
+
+ default:
+ panic("r10k pdcache line size %d",
+ mips_pdcache_line_size);
+ }
+ break;
#endif /* MIPS3 || MIPS4 */
default:
***************
*** 716,721 ****
--- 759,805 ----
mips_cache_ops.mco_sdcache_wb_range =
r5k_sdcache_wb_range;
break;
+ case MIPS_R10000:
+ switch (mips_sdcache_ways) {
+ case 2:
+ switch (mips_sdcache_line_size) {
+ case 64:
+ mips_cache_ops.mco_sdcache_wbinv_all =
+ r4k_sdcache_wbinv_all_generic;
+ mips_cache_ops.mco_sdcache_wbinv_range =
+ r4k_sdcache_wbinv_range_generic;
+ mips_cache_ops.mco_sdcache_wbinv_range_index =
+ r4k_sdcache_wbinv_range_index_generic;
+ mips_cache_ops.mco_sdcache_inv_range =
+ r4k_sdcache_inv_range_generic;
+ mips_cache_ops.mco_sdcache_wb_range =
+ r4k_sdcache_wb_range_generic;
+ break;
+
+ case 128:
+ mips_cache_ops.mco_sdcache_wbinv_all =
+ r4k_sdcache_wbinv_all_128;
+ mips_cache_ops.mco_sdcache_wbinv_range =
+ r4k_sdcache_wbinv_range_128;
+ mips_cache_ops.mco_sdcache_wbinv_range_index =
+ r4k_sdcache_wbinv_range_index_128;
+ mips_cache_ops.mco_sdcache_inv_range =
+ r4k_sdcache_inv_range_128;
+ mips_cache_ops.mco_sdcache_wb_range =
+ r4k_sdcache_wb_range_128;
+ break;
+
+ default:
+ panic("r10k sdcache %d way line size %d",
+ mips_sdcache_ways, mips_sdcache_line_size);
+ }
+ break;
+
+ default:
+ panic("r10k sdcache %d way line size %d",
+ mips_sdcache_ways, mips_sdcache_line_size);
+ }
+ break;
#endif /* MIPS3 || MIPS4 */
default:
***************
*** 858,863 ****
--- 942,969 ----
}
}
}
+
+ void
+ mips4_get_cache_config(int csizebase)
+ {
+ uint32_t config = mips3_cp0_config_read();
+
+ mips_picache_size = MIPS4_CONFIG_CACHE_SIZE(config,
+ MIPS4_CONFIG_IC_MASK, csizebase, MIPS4_CONFIG_IC_SHIFT);
+ mips_picache_line_size = 64; /* 64 Byte */
+
+ mips_pdcache_size = MIPS4_CONFIG_CACHE_SIZE(config,
+ MIPS4_CONFIG_DC_MASK, csizebase, MIPS4_CONFIG_DC_SHIFT);
+ mips_pdcache_line_size = 32; /* 32 Byte */
+
+ mips_cache_alias_mask =
+ ((mips_pdcache_size / mips_pdcache_ways) - 1) & ~(PAGE_SIZE - 1);
+ mips_cache_prefer_mask =
+ max(mips_pdcache_size, mips_picache_size) - 1;
+
+ mips_sdcache_line_size = MIPS4_CONFIG_CACHE_L2_LSIZE(config);
+ }
+
#endif /* MIPS3 || MIPS4 */
#endif /* MIPS1 || MIPS3 || MIPS4 */
diff -cr arch/mips/mips/cache_r10k.c /home/ax/union_src/sys/arch/mips/mips/cache_r10k.c
*** arch/mips/mips/cache_r10k.c Sat Aug 23 01:45:57 2003
--- /home/ax/union_src/sys/arch/mips/mips/cache_r10k.c Sat Aug 23 01:52:55 2003
***************
*** 0 ****
--- 1,140 ----
+ /* $NetBSD: $ */
+
+ /*
+ * Copyright (c) 2003 KIYOHARA Takashi <kiyohara@kk.iij4u.or.jp>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ #include <sys/cdefs.h>
+
+ #include <sys/param.h>
+
+ #include <mips/cache.h>
+ #include <mips/cache_r4k.h>
+ #include <mips/cache_r5k.h>
+ #include <mips/cache_r10k.h>
+ #include <mips/locore.h>
+
+ /*
+ * Cache operations for R10000-style caches:
+ *
+ * - 2-way set-associative
+ * - Write-back
+ * - Virtually indexed, physically tagged
+ *
+ */
+
+ #define round_line(x) (((x) + 63) & ~63)
+ #define trunc_line(x) ((x) & ~63)
+
+ __asm(".set mips3");
+
+ void
+ r10k_icache_sync_all_64(void)
+ {
+ vaddr_t va = MIPS_PHYS_TO_KSEG0(0);
+ vaddr_t eva = va + mips_picache_size;
+
+ /*
+ * Since we're hitting the whole thing, we don't have to
+ * worry about the 2 different "ways".
+ */
+
+ mips_dcache_wbinv_all();
+
+ __asm __volatile("sync");
+
+ while (va < eva) {
+ cache_r10k_op_32lines_64(va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
+ va += (32 * 64);
+ }
+ }
+
+ void
+ r10k_icache_sync_range_64(vaddr_t va, vsize_t size)
+ {
+ vaddr_t eva = round_line(va + size);
+
+ va = trunc_line(va);
+
+ mips_dcache_wb_range(va, (eva - va));
+
+ __asm __volatile("sync");
+
+ while ((eva - va) >= (32 * 64)) {
+ cache_r10k_op_32lines_64(va, CACHE_R4K_I|CACHEOP_R4K_HIT_INV);
+ va += (32 * 64);
+ }
+
+ while (va < eva) {
+ cache_op_r4k_line(va, CACHE_R4K_I|CACHEOP_R4K_HIT_INV);
+ va += 64;
+ }
+ }
+
+ void
+ r10k_icache_sync_range_index_64(vaddr_t va, vsize_t size)
+ {
+ vaddr_t w2va, eva, orig_va;
+
+ orig_va = va;
+
+ eva = round_line(va + size);
+ va = trunc_line(va);
+
+ mips_dcache_wbinv_range_index(va, (eva - va));
+
+ __asm __volatile("sync");
+
+ /*
+ * Since we're doing Index ops, we expect to not be able
+ * to access the address we've been given. So, get the
+ * bits that determine the cache index, and make a KSEG0
+ * address out of them.
+ */
+ va = MIPS_PHYS_TO_KSEG0(orig_va & mips_picache_way_mask);
+
+ eva = round_line(va + size);
+ va = trunc_line(va);
+ w2va = va + mips_picache_way_size;
+
+ while ((eva - va) >= (16 * 64)) {
+ cache_r10k_op_16lines_64_2way(va, w2va,
+ CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
+ va += (16 * 64);
+ w2va += (16 * 64);
+ }
+
+ while (va < eva) {
+ cache_op_r4k_line( va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
+ cache_op_r4k_line(w2va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
+ va += 64;
+ w2va += 64;
+ }
+ }
+
+ void
+ r10k_pdcache_wb_range(vaddr_t va, vsize_t size)
+ {
+ /* R10000 processor does not support */
+ }
----Next_Part(Sat_Aug_23_02:14:07_2003_253)----