Subject: Re: netbsd on r5000 indy
To: Manuel Bouyer <bouyer@antioche.lip6.fr>
From: Christopher SEKIYA <wileyc@rezrov.net>
List: port-sgimips
Date: 01/29/2003 23:58:15
On Tue, Jan 28, 2003 at 03:49:20PM +0100, Manuel Bouyer wrote:
> cpu0: 512KB/32B direct-mapped write-back L2 Data cache
> cpu0: disabling IP22 SysAD L2 cache
> panic: TLB out of universe: ksp 0xc59abb98 epc 0x8829b15c vaddr 0xffffe000
> Stopped in pid 1 (init) at 0x88291b14: jr ra
> bdslot: nop
L2 cache brokenness. The following _may_ help:
* apply the patch appended, which enables r5k L2 cache support,
* fixup sgimips/sgimips/machdep.c/mips_machdep_cache_config() such that
the (mach_type == MACH_SGI_IP22) does the same as the #ifdef 1 bit
for the MACH_SGI_IP32 code.
Just a guess.
-- Chris
GPG key FEB9DE7F (91AF 4534 4529 4BCC 31A5 938E 023E EEFB FEB9 DE7F)
diff -urNbB /usr/local/src/netbsd-current/sys/arch/mips/conf/files.mips sys/arch/mips/conf/files.mips
--- /usr/local/src/netbsd-current/sys/arch/mips/conf/files.mips Sat Nov 16 05:18:12 2002
+++ sys/arch/mips/conf/files.mips Sat Jan 11 12:58:06 2003
@@ -45,6 +45,7 @@
file arch/mips/mips/cache_tx39_subr.S mips1 & enable_mips_tx3900
file arch/mips/mips/cache_r4k.c mips3 | mips4
file arch/mips/mips/cache_r5k.c mips3 | mips4
+file arch/mips/mips/cache_r5k_subr.S mips3 | mips4
file arch/mips/mips/cache_r5900.c mips3 & mips3_5900
file arch/mips/mips/cache_mipsNN.c mips32 | mips64
diff -urNbB /usr/local/src/netbsd-current/sys/arch/mips/include/cache_r4k.h sys/arch/mips/include/cache_r4k.h
--- /usr/local/src/netbsd-current/sys/arch/mips/include/cache_r4k.h Mon Nov 18 04:03:19 2002
+++ sys/arch/mips/include/cache_r4k.h Sat Jan 11 12:58:06 2003
@@ -357,29 +357,6 @@
void r4k_pdcache_inv_range_32(vaddr_t, vsize_t);
void r4k_pdcache_wb_range_32(vaddr_t, vsize_t);
-void r5k_icache_sync_all_32(void);
-void r5k_icache_sync_range_32(vaddr_t, vsize_t);
-void r5k_icache_sync_range_index_32(vaddr_t, vsize_t);
-
-void r5k_pdcache_wbinv_all_16(void);
-void r5k_pdcache_wbinv_all_32(void);
-void r4600v1_pdcache_wbinv_range_32(vaddr_t, vsize_t);
-void r4600v2_pdcache_wbinv_range_32(vaddr_t, vsize_t);
-void vr4131v1_pdcache_wbinv_range_16(vaddr_t, vsize_t);
-void r5k_pdcache_wbinv_range_16(vaddr_t, vsize_t);
-void r5k_pdcache_wbinv_range_32(vaddr_t, vsize_t);
-void r5k_pdcache_wbinv_range_index_16(vaddr_t, vsize_t);
-void r5k_pdcache_wbinv_range_index_32(vaddr_t, vsize_t);
-
-void r4600v1_pdcache_inv_range_32(vaddr_t, vsize_t);
-void r4600v2_pdcache_inv_range_32(vaddr_t, vsize_t);
-void r5k_pdcache_inv_range_16(vaddr_t, vsize_t);
-void r5k_pdcache_inv_range_32(vaddr_t, vsize_t);
-void r4600v1_pdcache_wb_range_32(vaddr_t, vsize_t);
-void r4600v2_pdcache_wb_range_32(vaddr_t, vsize_t);
-void r5k_pdcache_wb_range_16(vaddr_t, vsize_t);
-void r5k_pdcache_wb_range_32(vaddr_t, vsize_t);
-
void r4k_sdcache_wbinv_all_32(void);
void r4k_sdcache_wbinv_range_32(vaddr_t, vsize_t);
void r4k_sdcache_wbinv_range_index_32(vaddr_t, vsize_t);
diff -urNbB /usr/local/src/netbsd-current/sys/arch/mips/include/cache_r5k.h sys/arch/mips/include/cache_r5k.h
--- /usr/local/src/netbsd-current/sys/arch/mips/include/cache_r5k.h Thu Jan 1 09:00:00 1970
+++ sys/arch/mips/include/cache_r5k.h Sat Jan 11 12:58:06 2003
@@ -0,0 +1,71 @@
+/* $NetBSD: cache_r4k.h,v 1.8 2002/11/17 06:40:43 simonb Exp $ */
+
+/*
+ * Copyright 2001 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if defined(_KERNEL) && !defined(_LOCORE)
+
+void r5k_icache_sync_all_32(void);
+void r5k_icache_sync_range_32(vaddr_t, vsize_t);
+void r5k_icache_sync_range_index_32(vaddr_t, vsize_t);
+
+void r5k_pdcache_wbinv_all_16(void);
+void r5k_pdcache_wbinv_all_32(void);
+void r4600v1_pdcache_wbinv_range_32(vaddr_t, vsize_t);
+void r4600v2_pdcache_wbinv_range_32(vaddr_t, vsize_t);
+void vr4131v1_pdcache_wbinv_range_16(vaddr_t, vsize_t);
+void r5k_pdcache_wbinv_range_16(vaddr_t, vsize_t);
+void r5k_pdcache_wbinv_range_32(vaddr_t, vsize_t);
+void r5k_pdcache_wbinv_range_index_16(vaddr_t, vsize_t);
+void r5k_pdcache_wbinv_range_index_32(vaddr_t, vsize_t);
+
+void r4600v1_pdcache_inv_range_32(vaddr_t, vsize_t);
+void r4600v2_pdcache_inv_range_32(vaddr_t, vsize_t);
+void r5k_pdcache_inv_range_16(vaddr_t, vsize_t);
+void r5k_pdcache_inv_range_32(vaddr_t, vsize_t);
+void r4600v1_pdcache_wb_range_32(vaddr_t, vsize_t);
+void r4600v2_pdcache_wb_range_32(vaddr_t, vsize_t);
+void r5k_pdcache_wb_range_16(vaddr_t, vsize_t);
+void r5k_pdcache_wb_range_32(vaddr_t, vsize_t);
+
+void r5k_enable_sdcache(void);
+
+void r5k_sdcache_wbinv_all(void);
+void r5k_sdcache_wbinv_range(vaddr_t, vsize_t);
+void r5k_sdcache_wbinv_rangeall(vaddr_t, vsize_t);
+void r5k_sdcache_inv_range(vaddr_t, vsize_t);
+void r5k_sdcache_wb_range(vaddr_t, vsize_t);
+
+#endif /* _KERNEL && !_LOCORE */
diff -urNbB /usr/local/src/netbsd-current/sys/arch/mips/include/cpuregs.h sys/arch/mips/include/cpuregs.h
--- /usr/local/src/netbsd-current/sys/arch/mips/include/cpuregs.h Sat Jan 11 04:04:14 2003
+++ sys/arch/mips/include/cpuregs.h Sat Jan 11 12:58:06 2003
@@ -325,6 +325,9 @@
/* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */
#define MIPS3_CONFIG_SE 0x00001000
+/* L2 cache-present bit for 5000SC */
+#define MIPS3_CONFIG_SC_ENABLE 0x00001000
+
/* Block ordering: 0: sequential, 1: sub-block */
#define MIPS3_CONFIG_EB 0x00002000
diff -urNbB /usr/local/src/netbsd-current/sys/arch/mips/mips/cache.c sys/arch/mips/mips/cache.c
--- /usr/local/src/netbsd-current/sys/arch/mips/mips/cache.c Sat Jan 11 04:04:14 2003
+++ sys/arch/mips/mips/cache.c Sat Jan 11 12:58:06 2003
@@ -82,7 +82,8 @@
#endif
#ifdef MIPS3_PLUS
-#include <mips/cache_r4k.h> /* includes r5k and greater */
+#include <mips/cache_r4k.h>
+#include <mips/cache_r5k.h>
#endif
#if defined(MIPS32) || defined(MIPS64)
@@ -644,10 +645,6 @@
#ifdef ENABLE_MIPS_R4700
case MIPS_R4700:
#endif
-#ifndef ENABLE_MIPS_R3NKK
- case MIPS_R5000:
-#endif
- case MIPS_RM5200:
switch (mips_sdcache_ways) {
case 1:
switch (mips_sdcache_line_size) {
@@ -701,6 +698,22 @@
panic("r4k sdcache %d way line size %d",
mips_sdcache_ways, mips_sdcache_line_size);
}
+ break;
+#ifndef ENABLE_MIPS_R3NKK
+ case MIPS_R5000:
+#endif
+ case MIPS_RM5200:
+ printf("R5000/Rm5200 SCACHE\n");
+ mips_cache_ops.mco_sdcache_wbinv_all =
+ r5k_sdcache_wbinv_all;
+ mips_cache_ops.mco_sdcache_wbinv_range =
+ r5k_sdcache_wbinv_range;
+ mips_cache_ops.mco_sdcache_wbinv_range_index =
+ r5k_sdcache_wbinv_rangeall; /* XXX? */
+ mips_cache_ops.mco_sdcache_inv_range =
+ r5k_sdcache_wbinv_range;
+ mips_cache_ops.mco_sdcache_wb_range =
+ r5k_sdcache_wb_range;
break;
#endif /* MIPS3 || MIPS4 */
diff -urNbB /usr/local/src/netbsd-current/sys/arch/mips/mips/cache_r5k.c sys/arch/mips/mips/cache_r5k.c
--- /usr/local/src/netbsd-current/sys/arch/mips/mips/cache_r5k.c Sat Nov 9 04:03:23 2002
+++ sys/arch/mips/mips/cache_r5k.c Sat Jan 11 12:58:06 2003
@@ -39,6 +39,7 @@
#include <mips/cache.h>
#include <mips/cache_r4k.h>
+#include <mips/cache_r5k.h>
#include <mips/locore.h>
/*
@@ -581,3 +582,57 @@
#undef trunc_line16
#undef round_line
#undef trunc_line
+
+/*
+ * Cache operations for R5000-style secondary caches:
+ *
+ * - Direct-mapped
+ * - Write-through
+ * - Physically indexed, physically tagged
+ *
+ */
+
+
+__asm(".set mips3");
+
+#define R5K_Page_Invalidate_S 0x17
+
+void
+r5k_sdcache_wbinv_all(void)
+{
+ vaddr_t va = MIPS_PHYS_TO_KSEG0(0);
+ vaddr_t eva = va + mips_sdcache_size;
+
+ while (va < eva) {
+ cache_op_r4k_line(va, R5K_Page_Invalidate_S);
+ va += (128 * 32);
+ }
+}
+
+/* XXX: want wbinv_range_index here instead? */
+void
+r5k_sdcache_wbinv_rangeall(vaddr_t va, vsize_t size)
+{
+ r5k_sdcache_wbinv_all();
+}
+
+#define round_page(x) (((x) + (128 * 32 - 1)) & ~(128 * 32 - 1))
+#define trunc_page(x) ((x) & ~(128 * 32 - 1))
+
+void
+r5k_sdcache_wbinv_range(vaddr_t va, vsize_t size)
+{
+ vaddr_t eva = round_page(va + size);
+ va = trunc_page(va);
+
+ while (va < eva) {
+ cache_op_r4k_line(va, R5K_Page_Invalidate_S);
+ va += (128 * 32);
+ }
+}
+
+void
+r5k_sdcache_wb_range(vaddr_t va, vsize_t size)
+{
+ /* Write-through cache, no need to WB */
+}
diff -urNbB /usr/local/src/netbsd-current/sys/arch/mips/mips/cache_r5k_subr.S sys/arch/mips/mips/cache_r5k_subr.S
--- /usr/local/src/netbsd-current/sys/arch/mips/mips/cache_r5k_subr.S Thu Jan 1 09:00:00 1970
+++ sys/arch/mips/mips/cache_r5k_subr.S Sat Jan 11 12:58:06 2003
@@ -0,0 +1,77 @@
+/* $NetBSD$ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permited provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <mips/asm.h>
+#include <mips/cpuregs.h>
+#include <mips/cache_r4k.h>
+#include <mips/cache_r5k.h>
+
+ .set mips3
+ .set noreorder
+
+/*
+ * r5k_enable_sdcache:
+ *
+ * Enable and clear out the R5k secondary (unified) cache.
+ */
+LEAF_NOPROFILE(r5k_enable_sdcache)
+ lw t2, _C_LABEL(mips_sdcache_size)
+ la t1, MIPS_KSEG0_START
+
+ beq t2, zero, 3f # if no sdcache, we can bail now
+ nop
+
+ add t2, t1, t2
+
+ la v0, 1f
+ or v0, MIPS_KSEG1_START
+
+ j v0 # run the rest from uncached space
+ nop
+
+1:
+ mfc0 v0, MIPS_COP_0_CONFIG
+ or v1, v0, MIPS3_CONFIG_SC_ENABLE
+ mtc0 v1, MIPS_COP_0_CONFIG # enable the secondary cache
+ nop
+ nop
+ nop
+
+2:
+ cache 0x17, 0(t1) # 0x17 == Page_Invalidate_SD
+ addiu t1, t1, 4096
+
+ sltu v0, t1, t2
+ bne v0, zero, 2b
+ nop
+
+3:
+ j ra
+ nop
+END(r5k_enable_sdcache)
+
diff -urNbB /usr/local/src/netbsd-current/sys/arch/mips/mips/pmap.c sys/arch/mips/mips/pmap.c
--- /usr/local/src/netbsd-current/sys/arch/mips/mips/pmap.c Tue Jan 7 12:31:10 2003
+++ sys/arch/mips/mips/pmap.c Sat Jan 11 12:58:06 2003
@@ -266,7 +266,6 @@
void mips_dump_segtab(struct proc *);
#endif
-#if defined(MIPS3_L2CACHE_ABSENT)
/*
* Flush virtual addresses associated with a given physical address
*/
@@ -290,7 +289,6 @@
}
#endif
}
-#endif /* MIPS3_L2CACHE_ABSENT */
/*
* Bootstrap the system enough to run with virtual memory.
@@ -1578,6 +1576,10 @@
mips_pagezero((caddr_t)MIPS_PHYS_TO_KSEG0(phys));
+#if 1 /* XXXrkb: R5kSC hacks */
+ mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(phys), NBPG);
+#endif
+
#if defined(MIPS3_PLUS) && defined(MIPS3_L2CACHE_ABSENT) /* XXX mmu XXX */
/*
* If we have a virtually-indexed, physically-tagged WB cache,
@@ -1611,6 +1613,11 @@
printf("pmap_copy_page(%lx) dst nonphys\n", (u_long)dst);
#endif
+#if 1 /* XXXrkb: R5kSC hacks */
+ mips_flushcache_allpvh(src);
+/* mips_flushcache_allpvh(dst); */
+#endif
+
#if defined(MIPS3_PLUS) && defined(MIPS3_L2CACHE_ABSENT) /* XXX mmu XXX */
/*
* If we have a virtually-indexed, physically-tagged cache,
@@ -1634,6 +1641,11 @@
mips_pagecopy((caddr_t)MIPS_PHYS_TO_KSEG0(dst),
(caddr_t)MIPS_PHYS_TO_KSEG0(src));
+
+#if 1 /* XXXrkb: R5kSC hacks */
+ mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(src), NBPG);
+ mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(dst), NBPG);
+#endif
#if defined(MIPS3_PLUS) && defined(MIPS3_L2CACHE_ABSENT) /* XXX mmu XXX */
/*
diff -urNbB /usr/local/src/netbsd-current/sys/arch/sgimips/sgimips/machdep.c sys/arch/sgimips/sgimips/machdep.c
--- /usr/local/src/netbsd-current/sys/arch/sgimips/sgimips/machdep.c Sat Jan 11 04:04:21 2003
+++ sys/arch/sgimips/sgimips/machdep.c Sat Jan 11 12:58:06 2003
@@ -71,7 +71,7 @@
#include <mips/locore.h>
#include <mips/cache.h>
-#if 0
+#if 1
#include <mips/cache_r5k.h>
#endif
@@ -917,7 +917,7 @@
if (mach_type == MACH_SGI_IP32)
{
-#if 1
+#if 0
/* L2 cache does not work on IP32 (yet) */
mips_sdcache_size = 0;
mips_sdcache_line_size = 0;