Subject: Re: pmap_{zero|copy}_page() re-engineering
To: None <port-sgimips@netbsd.org>
From: Toru Nishimura <locore32@gaea.ocn.ne.jp>
List: port-sgimips
Date: 01/09/2003 01:01:58 
Urr, correction...

> - L2 cache of R5000/RM5200 has the same line size of L1.  This
> means L2 cache line, which is physical address indexed, needs
not
> to worry about the cache line content is "teared apart" to distinct
> L1 cache lines.

Toru Nishimura