Some notes on MIPS processors.

- R5000 is R4600/R4700 derivative designed by QED team.
(quite straight technological path thru 4600->5000->52xx->7000)
- IDT and NEC manufactured it.
- Vr5500 has little to do with R5000.  It has a distinct core design.
It's a logical successor of R4300i/Vr4300 and Vr5432. 
- Vr5500 has no provision for external cache.  The bit of configuration
register $16 is wired zero.  Vr7701 will have on-chip L2.
- The bit should be considered as "External Cache Enable"

Toru Nishimura/ALKYL Technology/www.alkyltechnology.com

+/* 
+ * XXXrkb: should we put the following into a different namespace, seeing
+ * as it breaks the rule of being R/O (it's actually R/W) and it's only
+ * there on the R5k, QED Rm52xx and NEC Vr5000 (which, AFAIK is just a
+ * R5k made/sold by NEC instead of MIPS)?  Actually, not sure of about
+ * the NEC Vr5500 (no provision for external cache?); on the QED Rm7k,
+ * this controls L3 rather than L2 cache enable.
+ */
+/* L2 cache-enable bit for R5000/Rm52xx */
+#define MIPS3_CONFIG_SC_ENABLE 0x00001000