Subject: Adding R5k/Rm5200 L2 cache enable bit to CP0_CONFIG
To: None <port-mips@netbsd.org>
From: Rafal Boni <rafal@attbi.com>
List: port-sgimips
Date: 01/03/2003 05:18:44
--==_Exmh_58867018916P
Content-Type: text/plain; charset=us-ascii
Folks:
To get the R5k/Rm5200 with L2 cache working, one first needs to
enable the L2 cache in software; I've got changes to do that,
which I'll send under separate cover, but right now I'd like
to add enough code to have the MIPS cache code deal with the
situation where the L2 cache is present but disabled.
To do this, I've added a MIPS3_CONFIG_SC_ENABLE bit to the
MIPS cpuregs.h header file; this name is bad for several
reaons:
* That bit isn't present in generic MIPS3 CPUs; it's
specific to R5k/Rm52xx/Rm7k and maybe some others.
On the Rm7k, it in fact controls L3 cache, not L2.
* I believe the bit is called `SE' in the R5k docs
and/or the Rm52xx docs.
Do folks out there have a suggested name for this bit which
would fit both the above constraints, or should I leave it
as MIPS3_CONFIG_SC_ENABLE or change it to MIPS3_CONFIG_SE
so it at least matches the docs? (I prefer the latter of
the two names).
As you can see this patch is a bit of a WIP (I've got more
changes in comments than actual code 8-); I plan on cleaning
up the comments before I commit...
Diff attached below. Thanks to Chris Sekiya for the initial
version of all the R5k cache code which propelled this in the
right direction 8-)
--rafal
Index: include/cpuregs.h
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/include/cpuregs.h,v
retrieving revision 1.58
diff -b -u -p -r1.58 cpuregs.h
--- include/cpuregs.h 2002/11/15 01:15:11 1.58
+++ include/cpuregs.h 2003/01/03 10:13:45
@@ -322,6 +322,17 @@
((base) << (((config) & (mask)) >> (shift)))
#endif
+/*
+ * XXXrkb: should we put the following into a different namespace, seeing
+ * as it breaks the rule of being R/O (it's actually R/W) and it's only
+ * there on the R5k, QED Rm52xx and NEC Vr5000 (which, AFAIK is just a
+ * R5k made/sold by NEC instead of MIPS)? Actually, not sure of about
+ * the NEC Vr5500 (no provision for external cache?); on the QED Rm7k,
+ * this controls L3 rather than L2 cache enable.
+ */
+/* L2 cache-enable bit for R5000/Rm52xx */
+#define MIPS3_CONFIG_SC_ENABLE 0x00001000
+
/* Block ordering: 0: sequential, 1: sub-block */
#define MIPS3_CONFIG_EB 0x00002000
Index: mips/cache.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/cache.c,v
retrieving revision 1.15
diff -b -u -p -r1.15 cache.c
--- mips/cache.c 2002/12/17 12:04:30 1.15
+++ mips/cache.c 2003/01/03 10:13:46
@@ -797,6 +797,7 @@ tx39_cache_config_write_through(void)
void
mips3_get_cache_config(int csizebase)
{
+ int has_sdcache_enable = 0;
uint32_t config = mips3_cp0_config_read();
mips_picache_size = MIPS3_CONFIG_CACHE_SIZE(config,
@@ -814,10 +815,29 @@ mips3_get_cache_config(int csizebase)
mips_cache_prefer_mask =
max(mips_pdcache_size, mips_picache_size) - 1;
+ if (MIPS_PRID_IMPL(cpu_id) == MIPS_R5000 ||
+ MIPS_PRID_IMPL(cpu_id) == MIPS_RM5200)
+ has_sdcache_enable = 1;
+
+ /*
+ * If CPU has a software-enabled L2 cache, check both if it's
+ * present and if it's enabled before making assumptions the
+ * L2 is usable. If the L2 is disabled, we treat it the same
+ * as if there were no L2 cache.
+ */
if ((config & MIPS3_CONFIG_SC) == 0) {
- mips_sdcache_line_size = MIPS3_CONFIG_CACHE_L2_LSIZE(config);
+ if (has_sdcache_enable == 0 ||
+ (has_sdcache_enable && (config & MIPS3_CONFIG_SC_ENABLE))) {
+ mips_sdcache_line_size =
+ MIPS3_CONFIG_CACHE_L2_LSIZE(config);
if ((config & MIPS3_CONFIG_SS) == 0)
mips_scache_unified = 1;
+ } else {
+#define CACHE_DEBUG
+#ifdef CACHE_DEBUG
+ printf("MIPS3 Secondary cache detected, but is disabled -- WILL NOT ENABLE!\n");
+#endif /* CACHE_DEBUG */
+ }
}
}
#endif /* MIPS3 || MIPS4 */
----
Rafal Boni rafal@attbi.com
We are all worms. But I do believe I am a glowworm. -- Winston Churchill
--==_Exmh_58867018916P
Content-Type: application/pgp-signature
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Content-Type: text/plain; charset=us-ascii
Folks:
To get the R5k/Rm5200 with L2 cache working, one first needs to
enable the L2 cache in software; I've got changes to do that,
which I'll send under separate cover, but right now I'd like
to add enough code to have the MIPS cache code deal with the
situation where the L2 cache is present but disabled.
To do this, I've added a MIPS3_CONFIG_SC_ENABLE bit to the
MIPS cpuregs.h header file; this name is bad for several
reaons:
* That bit isn't present in generic MIPS3 CPUs; it's
specific to R5k/Rm52xx/Rm7k and maybe some others.
On the Rm7k, it in fact controls L3 cache, not L2.
* I believe the bit is called `SE' in the R5k docs
and/or the Rm52xx docs.
Do folks out there have a suggested name for this bit which
would fit both the above constraints, or should I leave it
as MIPS3_CONFIG_SC_ENABLE or change it to MIPS3_CONFIG_SE
so it at least matches the docs? (I prefer the latter of
the two names).
As you can see this patch is a bit of a WIP (I've got more
changes in comments than actual code 8-); I plan on cleaning
up the comments before I commit...
Diff attached below. Thanks to Chris Sekiya for the initial
version of all the R5k cache code which propelled this in the
right direction 8-)
- --rafal
Index: include/cpuregs.h
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/include/cpuregs.h,v
retrieving revision 1.58
diff -b -u -p -r1.58 cpuregs.h
- --- include/cpuregs.h 2002/11/15 01:15:11 1.58
+++ include/cpuregs.h 2003/01/03 10:13:45
@@ -322,6 +322,17 @@
((base) << (((config) & (mask)) >> (shift)))
#endif
+/*
+ * XXXrkb: should we put the following into a different namespace, seeing
+ * as it breaks the rule of being R/O (it's actually R/W) and it's only
+ * there on the R5k, QED Rm52xx and NEC Vr5000 (which, AFAIK is just a
+ * R5k made/sold by NEC instead of MIPS)? Actually, not sure of about
+ * the NEC Vr5500 (no provision for external cache?); on the QED Rm7k,
+ * this controls L3 rather than L2 cache enable.
+ */
+/* L2 cache-enable bit for R5000/Rm52xx */
+#define MIPS3_CONFIG_SC_ENABLE 0x00001000
+
/* Block ordering: 0: sequential, 1: sub-block */
#define MIPS3_CONFIG_EB 0x00002000
Index: mips/cache.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/cache.c,v
retrieving revision 1.15
diff -b -u -p -r1.15 cache.c
- --- mips/cache.c 2002/12/17 12:04:30 1.15
+++ mips/cache.c 2003/01/03 10:13:46
@@ -797,6 +797,7 @@ tx39_cache_config_write_through(void)
void
mips3_get_cache_config(int csizebase)
{
+ int has_sdcache_enable = 0;
uint32_t config = mips3_cp0_config_read();
mips_picache_size = MIPS3_CONFIG_CACHE_SIZE(config,
@@ -814,10 +815,29 @@ mips3_get_cache_config(int csizebase)
mips_cache_prefer_mask =
max(mips_pdcache_size, mips_picache_size) - 1;
+ if (MIPS_PRID_IMPL(cpu_id) == MIPS_R5000 ||
+ MIPS_PRID_IMPL(cpu_id) == MIPS_RM5200)
+ has_sdcache_enable = 1;
+
+ /*
+ * If CPU has a software-enabled L2 cache, check both if it's
+ * present and if it's enabled before making assumptions the
+ * L2 is usable. If the L2 is disabled, we treat it the same
+ * as if there were no L2 cache.
+ */
if ((config & MIPS3_CONFIG_SC) == 0) {
- - mips_sdcache_line_size = MIPS3_CONFIG_CACHE_L2_LSIZE(config);
+ if (has_sdcache_enable == 0 ||
+ (has_sdcache_enable && (config & MIPS3_CONFIG_SC_ENABLE))) {
+ mips_sdcache_line_size =
+ MIPS3_CONFIG_CACHE_L2_LSIZE(config);
if ((config & MIPS3_CONFIG_SS) == 0)
mips_scache_unified = 1;
+ } else {
+#define CACHE_DEBUG
+#ifdef CACHE_DEBUG
+ printf("MIPS3 Secondary cache detected, but is disabled -- WILL NOT ENABLE!\n");
+#endif /* CACHE_DEBUG */
+ }
}
}
#endif /* MIPS3 || MIPS4 */
- ----
Rafal Boni rafal@attbi.com
We are all worms. But I do believe I am a glowworm. -- Winston Churchill
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.0.6 (NetBSD)
Comment: Exmh version 2.5 07/13/2001
iD8DBQE+FWOEEeBxM8fTAkwRAjoPAKCeomxf8345Cmq7fL7yrIMQLcePKQCfRKtc
XX+wWI50S7vsbs2JpA7CUfI=
=btxp
-----END PGP SIGNATURE-----
--==_Exmh_58867018916P--