In message <000801c2a255$379ab1c0$0d00a8c0@paq5>, you write: 

-> > FWIW, IDT's R5000 docs are still online at:
-> 
-> Um,  mystery insolved.   The IDT does not mention about the
-> secondary cache tag design and how addess coded performed.
-> RM5200 UM describes the 2ndary cache architecture in defnite
-> figures.   I can see R5000 SC controlling pin out is identical to
-> RM527x.  On the other hand, JP version of NEC Vr5000
-> provides (very confusing) 2nd cache tag figure which does not
-> match to RM527x.

Unfortunately, what you say about Vr5000 is true of not only the
Japanese but the English version as well... At some point it will
come down to just having to write the code and attempt to verify
that behaviour is sane across both real R5000 and Rm527x.

--rafal

----
Rafal Boni                                                     rafal@attbi.com
  We are all worms.  But I do believe I am a glowworm.  -- Winston Churchill