"Rafal Boni" <rafal@attbi.com> replied;

> Maybe I'm missing something, but I think the above snippet says that the
> secondary cache *is* actually physically indexed as described in the PMC
> Rm52xx docs.

It's my surprise R5000 doco insists itself virtual address index.  I spent a
while to figure out how the L2 SRAM was drived looking at chip wiring.
No definite clue from it.  (From designers' point of view, VA indexed
L2 is very questionable...)

> -> - I guess L2 cache is not properly initialized before use.  Then processor
> -> gets confused and posts cache error exception (SIDX/PIDX value may
> -> help).   Please comb through PMC-Sierra Knowledge Base.  I thought
> -> there was a clue around there.
> 
> That was my guess as well, but I had been promising to put up some code and
> unfortunately knew I wouldn't have a lot of time to play with it this week,
> so I figured I'd put up what I had with the above caveat...

I stepped across a KB item which mentions to cache error exception which
mandates L2 initialization.  It's not about R5000, but may help.

Toru Nishimura/ALKYL Technology