At 7:54 PM -0500 11/26/02, Rafal Boni wrote:
>In message <p05200d05ba09babea0ad@[192.168.0.207]>, you write:
>
>-> I'm running into a few weird issues with my 180Mhz O2 w/o secondary
>-> cache.
>
>Bonus: you may actually have some luck with a SC-less O2.  We have no
>code to drive the SC correctly, so all SC models blow chunks early on.

Yes, I have a 180/512k processor module that I've tried with 
obviously no success. Isn't it possible to disable the secondary 
cache on these? <flipping through "See MIPS Run"...>

>->       First of all when the machine boots cold, the kernel comes all
>-> the way up perfectly. On any warm reboot, it panic's in
>-> macepci_conf_read(), apparently the PERR_MEMORY_ADDR bit is set in
>-> the PCI_ERROR_FLAGS register. Which leads me to believe somewhere in
>-> PCI land there is something not getting (re)initialized properly?
>-> I have an fxp card installed into the slot. Has anyone else seen this?
>
>There is much broken in the current O2 code; Chris Sekiya re-did much
>of the PCI code and I've hacked on that to the point where I actually
>mounted root via a PCI-X Intel GigE card the other day (I've been using
>a RealTek for a while; a 3c905 was slightly harder to get working, and
>I don't recall if the fxp just worked or not).

I've successfully booted multi-user using the fxp card. (Let me know 
if anyone wants the 'dmesg') But of course, it's only short lived due 
to the hanging problem.

>  Unfortunately, none of
>that code is in the tree yet.  Maybe I'll try and do a mini-sync over
>the Thanksgiving holiday (ie, this weekend for the non-US folks out
>there 8-).

That would be great! Is Chris (or yourself) making it available 
somewhere right now?

>-> Also, when it does boot successfully (/ on NFS), after an unknown
>-> period of sitting idle, the machine becomes almost totally unresponsive,
>-> but it's not completely locked up (I wrote a routine to cycle though
>-> colors on the front panel led so I could see if interrupts were
>-> still being delivered). Has anyone run into this?
>
>You're probably not getting KB/serial/... interrupts, as the interrupt
>code currently in-tree (some have said "what interrupt code" 8-) is
>lacking to say the least.  I don't yet have better code, but I do have
>some icky hacks to get serial mostly working with the current code.

That makes sense, if/when I get some time, I'll poke around and see 
what I can find. And yes, I noticed the lack of interrupt code in my 
trying to get the mec0 working. :-) Either way I'm really excited 
about getting the O2 going, I just wish I had more time!

Thanks,
--josh