On Sun, Nov 25, 2001 at 09:05:41PM -0600, Scott G. Akmentins-Taylor wrote:

> It just hangs.  Anyone have a suggestion?

(snip)

> cpu0: 512KB/32B direct-mapped write-back L2 Data cache

"options MIPS3_L2CACHE_ABSENT" no longer works.  I've attached a VERY quick-and-
dirty patch that disables the recent, sgimips-local change.  This works for me.

The true cause, I think, is that the SysAD cache primitives are wrong.
Comparing the NetBSD code with the linux code, the only difference is the
numbers of nops in the prologue (three versus linux's four), but adding it
in didn't work for me.  I'm not smart enough to troubleshoot cache stuff :)

-- Chris

--- /usr/src/sys/arch/sgimips/sgimips/ip22.c    Fri Nov 16 05:11:55 2001
+++ ip22.c      Sun Nov 25 22:11:04 2001
@@ -452,11 +452,15 @@
         * If we don't have an R4000-style cache, then initialize the
         * IP22 SysAD L2 cache.
         */
+#if defined(L2_CACHE_ACTUALLY_WORKS)
        if (mips_sdcache_line_size == 0) {
+#endif
                /* XXX */
                printf("%s: disabling IP22 SysAD L2 cache\n", self->dv_xname);
                ip22_sdcache_disable();
+#if defined(L2_CACHE_ACTUALLY_WORKS)
        }
+#endif
 }
 
 #endif /* IP22 */

diff -urNbB /usr/src/sys/arch/sgimips/sgimips/cpu.c cpu.c
--- /usr/src/sys/arch/sgimips/sgimips/cpu.c     Wed Nov 21 04:52:10 2001
+++ cpu.c       Sun Nov 25 22:14:46 2001
@@ -62,6 +62,8 @@
 {
        struct device *self = atc->atc_cookie;
 
+       return;
+
        if (comp->Class != COMPONENT_CLASS_CacheClass)
                return;