On Thu, Apr 26, 2001 at 11:28:27AM -0700, Jeffrey M. Smith wrote:
> Rafal Boni wrote:
> > 
> > Does anyone out there have any info on how one is supposed to drive the L2
> > cache on an Indy/Indigo2?  I've heard Soren say that the L2 cache on these

I don't really know much more than is, er, documented in linux'
arch/mips/sgi/kernel/indy_sc.c .

> > boxes is somehow special and needs to be driven somewhat differently than
> > one would expect to drive it (well, I would exect it to be driven via the
> > 'cache op_SD' instructions, maybe others have other expectations 8-).
> > 
> > Or is this all only true for R4600 and R5000 parts?  (I've got a R4400SC).
> 
> I think this is the only the QED (R4600 and R5000) parts.  The R4400SC
> should act a lot like the pmax R4[04]00SC and use the cache ops defined
> in the R4000 spec.

This is my understanding too.

> I don't remember exactly how the R4600 S cache works.  It was done on
> the sysAD bus w/o any internal processor support.  The R5000 I think
> added some signals to make this type of cache work with less glue logic.

I believe that the special method used for the R4600 also works
for the R5000 at least. Don't know if the R5000 version can also
use a saner style.


-- 
Soren