Re: Allwinner D1

[Rui-Xiang Guo <rxg%lavabit.com@localhost>]

On Wed, Feb 05, 2025 at 07:09:58PM +0000, Nick Hudson wrote:
> On 05/02/2025 03:44, Rui-Xiang Guo wrote:
> > On Sat, Feb 01, 2025 at 01:52:17PM +0800, Rui-Xiang Guo wrote:
> > > After enabling clint in the firmware instead of attaching sunxitimer,
> > > the host controller starts activities but can't detect the card.
> > > [...]
> > > [   1.6914471] sunximmc0: mmc intr idst=00000000 mint=00000004
> > > [   1.6914471] sunximmc0: mmc intr idst=00000000 mint=00000808
> > > [   1.6914471] sunximmc0: host controller error, mint=0x00000808
> > > [   1.7099755] sdmmc1: 4-bit width, 50.000 MHz
> > > [   1.7099755] sunximmc0: i/o error 5
> > > [   1.7099755] sunximmc0: update clock
> > > [   1.7220301] sdmmc0: sdmem_mem_send_scr: error = 5
> > > [   1.7220301] sdmmc0: SD_SEND_SCR send failed.
> > > [   1.7309457] sdmmc0: mem init failed
> > > [   1.7309457] sdmmc0: init failed
> > > [   1.7309457] sunximmc0: opcode 7 flags 0x0 data 0x0 datalen 0 blklen 0
> > > [   1.7439451] sunximmc0: cmdval = 80000000
> > > [   1.7439451] sunximmc0: mmc intr idst=00000000 mint=00000004
> > > [   1.7534039] sunximmc0: width = 1
> > > [   1.7534039] sunximmc0: update clock
> > > [...]
> > > The complete log is in:
> > > https://github.com/picohive/netbsd-mangopi-mq-pro/blob/main/boot-debug-mmc.log
> > > 
> > > and the diff:
> > > https://github.com/picohive/netbsd-mangopi-mq-pro/blob/main/sunxi_mmc.c.diff
> > 
> > Would it be related to pmap? OpenBSD's pmap contains special handling for the
> > T-Head cores.
> 
> oh, yeah. mostly likely.
> 
> t-head can do uncached mappings via PTE. I was hoping to get to this
> soon(ish)

I tried adding the following patches, but they did not help.

RCS file: /cvsroot/src/sys/arch/riscv/include/pte.h,v
retrieving revision 1.14
diff -u -p -r1.14 pte.h
--- include/pte.h       12 Oct 2024 12:27:33 -0000      1.14
+++ include/pte.h       8 Oct 2025 13:08:52 -0000
@@ -62,6 +62,11 @@ typedef uint32_t pd_entry_t;
 #define PTE_PBMT       __BITS(62, 61)  // Svpbmt
 #define PTE_reserved0  __BITS(60, 54)  //

+#define PTE_THEAD_SO   __BIT(63)
+#define PTE_THEAD_C    __BIT(62)
+#define PTE_THEAD_B    __BIT(61)
+#define PTE_THEAD_SH   __BIT(60)
+
 /* Software PTE bits. */
 #define        PTE_RSW         __BITS(9, 8)
 #define        PTE_WIRED       __BIT(9)

RCS file: /cvsroot/src/sys/arch/riscv/riscv/pmap_machdep.c,v
retrieving revision 1.21
diff -u -p -r1.21 pmap_machdep.c
--- riscv/pmap_machdep.c        13 Jul 2025 21:09:45 -0000      1.21
+++ riscv/pmap_machdep.c        8 Oct 2025 13:09:46 -0000
@@ -432,7 +432,15 @@ pmap_kenter_range(vaddr_t va, paddr_t pa
        while (sva < eva) {
                const size_t sidx = (sva >> vshift) & pdetab_mask;

-               l1_pte[sidx] = PA_TO_PTE(spa) | PTE_KERN | PTE_HARDWIRED | PTE_RW;
+               pd_entry_t pte = PA_TO_PTE(spa) | PTE_KERN | PTE_HARDWIRED | PTE_RW;
+               if (flags & PMAP_DEV)
+                       pte |= PTE_THEAD_SO | PTE_THEAD_SH;
+               else if (flags & PMAP_NOCACHE)
+                       pte |= PTE_THEAD_B | PTE_THEAD_SH;
+               else
+                       pte |= PTE_THEAD_C | PTE_THEAD_B | PTE_THEAD_SH;
+
+               l1_pte[sidx] = pte;
                spa += NBSEG;
                sva += NBSEG;
        }

-rxg