Hi!

While looking for the instabilities in amigappc, I'm more and more convinced
it has something to do with the MMU setup. The system hangs always happen
at alternating locations after the MMU is enabled. 

I wish I had a possibiliy to debug the type of crash at this early phase.

I'm using custom BAT-setup code, as oea_batinit() expects to find the RAM
with the kernel and exception vectors at 0x00000000, which is not the case
here.

As far as I understand, the purpose of battable in oea_machdep.c is to hold
the settings of DBATU and DBATL for any of the 16 256MB segments where a DSI
exception may occur. The dsitrap code will then randomly load DBAT2 or DBAT3
with the BAT-setting for the fault-address. Correct?

- This means that the BATs covering the kernel- and exception-vector regions
  should never be in DBAT2 or DBAT3, also because an ISI exception will
  never replace BATs?

- Is there any code which depends on IBAT0/DBAT0 being set to battable[0].
  Or battable[0] being cacheable and coherent RAM?

- Is it allowed to set DBAT0/DBAT1 and only IBAT1, leaving IBAT0 disabled?

- When should I enable caches? For me it would make sense to do it in
  locore after initppc(). But I saw ports to turn them on ealier, before
  BATs have been set up.

- Why is battable an array with 512 entries? 16 should be enough.

- Does the kernel work with exception vectors at 0xfff00000 at all? Are
  there any hidden dependencies?


After the BATs have been initialized pmap_bootstrap() is called to
initialize the segment registers as well. Maybe this leads too far, but how
do the SRs and the BATs play together? I know that the BATs have priority,
so there should be no need for using MMU-tables in the kernel (sorry if this
sounds stupid). MMU-tables will be used in user-mode, of course.

Will the kernel run with a va=pa mapping the whole time? What are KERNEL_SR
and KERNEL2_SR used for?


-- 
    _  Frank Wille (frank@phoenix.owl.de)
 _ //  http://sun.hasenbraten.de/~frank/
 \X/   Phx @ #AmigaGer