# Shigeyuki Fukushima 2006-05-07:
> > IMO, it's better to summarize how many possible 4xx CPU variants
> > should be handled in that layer, and then design structure for
> > each of them before implementing it. At least there is another
> > port for PPC405D5Xn core:
> > http://mail-index.netbsd.org/port-powerpc/2006/04/26/0000.html
> 
> I don't know the details of PPC405Core.

This is the core used by Xilinx in their Virtex-{2 Pro, 4} FPGAs.
The documentation is a bit incosistent about naming, IIRC I took
the "PPC405D5X{1,2}" label from their errata sheet.

The evbppc/virtex port is rather exotic WRT regular 4xx chips,
so it sounds fair to treat it as a special case. I'm probably
going to create custom plb/opb indirect-config implementations
for it, as simonb@ suggested -- it looks like the simplest
general-enough approach.

	-- Jachym