Jochen,
Recently someone pointed out that the CPU ID for 604e and 604ev were
incorrect, and Allen Briggs had posted a patch some time back for this. I
took his patch and added some tweaks for L2 cache and MHz testing on a few
more CPUs, and then sent it back to him. The Apple documents state that the
604ev in 9600s and the like have a 1MB pipeline burst "inline" L2 cache. I
took this to mean "backside" cache and so I included it in testing.
Unfortunately, shortly after the patch was committed a tester reported back
problems and I found that "inline" means neither on the motherboard nor
backside, so while it behaves and specs much like a backside cache, the
Special Purpose Register L2CR register is not implemented on the 604ev,
which is why you're seeing the trap that you are. I've attached two patches
that address this problem and one other problem with the 604 family. The
first patch removes the 604ev from having any backside cache from being
probed, and the second adds power save mode usage during Idle(). The second
patch has fixed a couple systems (mine included) that were having problems
with hanging when attaching scsibus. It is unclear as to the exact reason
this patch fixes the problem, but it would appear that one or more
exceptions under normal conditions are not being caught but do get caught
when in power save mode.

tim

Index: cpu_subr.c
===================================================================
RCS file: /cvsroot/src/sys/arch/powerpc/oea/cpu_subr.c,v
retrieving revision 1.16
diff -d -u -r1.16 cpu_subr.c
--- cpu_subr.c  8 Dec 2004 03:07:03 -0000       1.16
+++ cpu_subr.c  18 Dec 2004 12:13:01 -0000
@@ -448,8 +448,8 @@
                aprint_normal("%s: ", self->dv_xname);
                cpu_print_speed();

-               if (vers == MPC604ev || vers == MPC750 || vers == MPC7400 ||
-                   vers == IBM750FX || vers == MPC7410 || MPC745X_P(vers)) {
+               if (vers == MPC750 || vers == MPC7400 || vers == IBM750FX
+                        || vers == MPC7410 || MPC745X_P(vers)) {
                        if (MPC745X_P(vers)) {
                                cpu_config_l3cr(vers);
                        } else {


Index: cpu_subr.c
===================================================================
RCS file: /cvsroot/src/sys/arch/powerpc/oea/cpu_subr.c,v
retrieving revision 1.16
diff -d -u -r1.16 cpu_subr.c
--- cpu_subr.c  8 Dec 2004 03:07:03 -0000       1.16
+++ cpu_subr.c  20 Dec 2004 03:49:16 -0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpu_subr.c,v 1.16 2004/12/08 03:07:03 briggs Exp $     */
+/*     $NetBSD: cpu_subr.c,v 1.14 2004/06/26 21:48:30 kleink Exp $     */

 /*-
  * Copyright (c) 2001 Matt Thomas.
@@ -34,7 +34,7 @@
  */

 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.16 2004/12/08 03:07:03 briggs
Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.14 2004/06/26 21:48:30 kleink
Exp $");

 #include "opt_ppcparam.h"
 #include "opt_multiprocessor.h"
@@ -352,6 +352,15 @@
         * Configure power-saving mode.
         */
        switch (vers) {
+
+       case MPC604:
+       case MPC604e:
+       case MPC604ev:
+               /* does not have HID0 support settings */
+               /* can support MSR[POW] off */
+               powersave = 1;
+               break;
+
        case MPC603:
        case MPC603e:
        case MPC603ev: