Hi,

Frank van der Linden wrote:
> Eduardo and I are working on a port to a chip based on an older
> 40x core (the 401D2). This one has a cache line size of 16.

I'm fully aware of the 16 byte cache line size of the 40x processors
(apart from the 405).  That's the reason I introduced the CACHELINESIZE
sysctl in the first place (while doing a port to the IBM Network Station
300,
which I hope to integrate into our tree once I can find enough time to
clean it up).

However, are you really planning to run the same kernel on one of those
boxes
and on, say, a PowerMac?

> So, you need to check what the cacheline size is, and whether you
> can safely use dcbz at all time. This would mean 2 sysctl calls
> for userspace (or one sysarch cachectl query call getting some flags),
> and for the kernel that's 2 #defines at least, but quite possibly
> one of them should be a variable.

It only needs to be a variable, if you try to support CPUs with
different
cache line sizes with the same kernel.  Currently I don't see a need
for this.

Ciao,
Wolfgang
-- 
ws@TooLs.DE     Wolfgang Solfrank, TooLs GmbH 	+49-228-985800