Subject: Re: bzero.S and assym.h (Re: CVS commit: syssrc/sys/lib/libkern/arch/powerpc)
To: Greg Lehey <grog@lemis.com>
From: David Edelsohn <dje@watson.ibm.com>
List: port-powerpc
Date: 12/03/2001 20:44:30
>>>>> Greg Lehey writes:
Greg> In general the 60x range has 32 bytes cache lines, embedded processors
Greg> (40x and 80x) have 16 bytes, and the 64 bit processors have 128 byte
Greg> cache lines. There are exceptions, like the 405, which is a 64 bit
Greg> embedded processor and has 32 byte cache lines.
The PPC405 is a 32-bit embedded processor.
David