Hello,

[I'll stick my neck out on this, I can't find my 603* manuals. :-)]

I believe that the *BSD/PowerPC kernels should be able to run on 603 or
603e with a small change explained below.

As background, both the 603 and 603e handle misses to their VM
Translation Lookaside Buffers in software - the processor traps to a
small interrupt handler that either loads a new TLB entry or (if the
entry isn't found) fudges things so that it looks like a normal `page
fault'.  The code that handles these traps being contained in processor
interrupt tables (somewhere in the 0x000..0x2fff address range).

At present, the *BSD kernels overrides these trap handlers with a
generic `panic' trap handler.  I can see a number of solutions.

	1.	Initially, I'd suggest that machdep.c:initppc()
		be modified so that it doesn't write over the
		603/603e TLB trap handlers.
		If the OpenFirmware is running in virtual mode
		then it will have already installed those handlers
		for you.  However, if the OpenFirmware is running
		in real mode then all bets are off :-)

	2.	Later, the kernel can be modified so that it detects
		the processor and thence installs the approperiate
		TLB miss handler.
		The handler code is freely available from IBM/Mot's
		web sites, just make certain it is the most recent
		version.

Any one see problems with this theory?

	enjoy,
		Andrew