>>>>> Wolfgang Solfrank writes:

>> The primary difference between the 601 and later, pure-PowerPC chips
>> (603, 604, etc.) is in the supervisor mode.  The 601 has a real-time clock,
>> not a time base, plus other supervisor-mode register differences.  The 601
>> MMU is significantly different from that specified by the PowerPC
>> architecture.  Imprecise processor exceptions are different, the BAT
>> registers are different, ....

Wolfgang> Hmm, correct me if I'm wrong, but isn't the real-time clock in the 601 user
Wolfgang> visible?  At least the time base in the 603/604 is.

	Yes, the RTC is user-visible.  I am sorry if my choice of words
implied differently.  The RTC counts seconds and nanoseconds while the TB
counts "ticks" based on the chip clock frequency (which can be variable).
RTCL rollover is 999999999 while TBL rollover is 0xFFFFFFFF.

	Also, the POWER architecture (including 601) has a user-visible
decrementer register which the PowerPC architecture removes to better
support a virtualized processor.  The DEC changes at the "tick" rate on
PowerPC but corresponding to the nanosecond rate of the RTC on the 601.  The
RTC rate is implementation independent and guaranteed to increment at least
once every 10 "addi" instructions, no TB guarantee is made.

David
===============================================================================
David Edelsohn                                      T.J. Watson Research Center
dje@watson.ibm.com                                  P.O. Box 218
+1 914 945 4364 (TL 862)                            Yorktown Heights, NY 10598