> 	The PPC601 was based on the POWER architecture RSC implementation --
> basically taking that POWER architecture chip and ADDING the user-visible
> PowerPC instructions including single-precision floating point.  It can and
> does run pure PowerPC code, but also can run pure POWER architecture code,
> or a mixed set for optimal instruction choice.  The POWER MQ register also
> is present but can be ignored if only running PowerPC code.
> 
> 	The primary difference between the 601 and later, pure-PowerPC chips
> (603, 604, etc.) is in the supervisor mode.  The 601 has a real-time clock,
> not a time base, plus other supervisor-mode register differences.  The 601
> MMU is significantly different from that specified by the PowerPC
> architecture.  Imprecise processor exceptions are different, the BAT
> registers are different, ....

Hmm, correct me if I'm wrong, but isn't the real-time clock in the 601 user
visible?  At least the time base in the 603/604 is.

> 	In supervisor mode -- areas of concern to OS kernels -- the chip
> looks quite different from the PowerPC architecture.  In user mode, if one
> ignores the POWER architecture features, it looks like PowerPC.  Basically
> the 601 is a POWER architecture chip with a PowerPC veneer.  But MkLinux
> soon will have a PPC603 and PPC604 kernel, and already has a PPC601 kernel,
> so it should be easy to compare and implement the reversed transform that
> MkLinux team used.

If you are right about the 601 implementing the full PowerPC instruction set
(and I have no real reason to doubt this), then it shouldn't be too hard
to make the 601 work..., apart from the fact that currently NetBSD/powerpc
relies heavily on OpenFirmware, and afaik there is no 601 machine implementing
OpenFirmware.
--
ws@TooLs.DE     (Wolfgang Solfrank, TooLs GmbH) 	+49-228-985800