Re: Interested in USB for TURBOchannel (slhci at tc)?

[Felix Deichmann <m4j0rd0m0%gmail.com@localhost>]

2016-04-08 9:37 GMT+02:00 Tobias Nygren <tnn%netbsd.org@localhost>:
> This would be plenty of pins to bit-bang to an i2c daughter board
> with an environmental monitoring chip, watchdog timer, debug port or
> similar, which are the sort of applications I had in mind. I realize you
> want to keep cost down :)

Hm, I could also test out a simple 8-bit GPIO implementation by two
registers (direction + data input/output) in TC address space, if you
like. Would be easy to bit-bang I²C or SPI or both then with another
plethora of options, right? I think we already have a framework in the
code for it.
This could potentially be part of the project right from the start if
it fits into the (CPLD) design, for free. Thanks, great idea!

Re-using timing of the current TC implementation, a 25 MHz TC system
could theoretically achieve a GPIO toggling speed of 25 / 6 = 4.17 MHz
with optimal back-to-back transactions. Not bad!

For the GPIO pin header, I would then go for 2x10, with one row being
8x ground + two voltages, the other row for the GPIOs + two voltages
(3.3 V and 5 V probably most useful). This would also allow connecting
a longer IDC flat ribbon cable with pwr/gnd running over every other
wire. The CPLD can source/sink -4.0/8.0 mA per pin regarding TTL, and
has hysteresis on the inputs, so additional buffers are not necessary
I hope. Default is LVTTL I/O config, 5 V tolerant, which should be
perfect for most applications. As this will be an "expert" connector
of your choice not fitted per default, I would also not provide
additional protection (reverse voltage, overcurrent/-voltage, ESD,
...). Watch out! :)

Felix